[PATCH] D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

I see one problem with this.

If you take a look at for example SystemZRegisterInfo.td we got

  let Namespace = "SystemZ" in {
  def subreg_l32   : SubRegIndex<32, 0>;  // Also acts as subreg_ll32.
  def subreg_h32   : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
  def subreg_l64   : SubRegIndex<64, 0>;
  def subreg_h64   : SubRegIndex<64, 64>;
  def subreg_hh32  : ComposedSubRegIndex<subreg_h64, subreg_h32>;
  def subreg_hl32  : ComposedSubRegIndex<subreg_h64, subreg_l32>;
  }

And those compositions are quite nice to be able to specify manually (giving them a custom name).

But in the past we have also gotten warning if trying to add a composition like this

  def subreg_ll32  : ComposedSubRegIndex<subreg_l64, subreg_l32>;

I kind of liked that warning, because if you add such a composition (that happens to clash with the uncomposed subreg_l32) you would end up with identical, but different subregister indices. They will occupy space in the lane masks and will not be identified as being identical when for example comparing the subregister index enum values in the code.

Maybe it is a slightly different problem, but the above is the reason why we are using the same name as tablegen when creating the composed subregister indices.
So you could also get rid of the warning by doing:

  def subreg_h64_then_subreg_h32  : ComposedSubRegIndex<subreg_h64, subreg_h32>;

Although that won't give you the possibility to choose a custom name.

It would be nice to find a solution where we still could give a warning/error for the subreg_ll32 composition, while still being able to use a custom name (without a warning) for the subreg_hh32 composition.

Another idea is to allow some kind of aliases (I was thinking about that some time ago). Such as

  def subreg_ll32  : AliasedSubRegIndex<subreg_l32>;

or maybe

  def subreg_ll32  : ComposedSubRegIndexAlias<subreg_l64, subreg_l32>;

making it possible to use subreg_ll32 as a name in mir-files, td-files etc. But having subreg_ll32 and subreg_l32 mapping to the same enum value in subregister idx enum.
I guess debug/mir-printouts would pick the default name and not the alias. So that might be confusing of course.


Repository:
  rL LLVM

https://reviews.llvm.org/D50977