[PATCH] D48131: [RISCV] Implement codegen for cmpxchg on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

In https://reviews.llvm.org/D48131#1131431, @efriedma wrote:

> You can introduce a target-specific SelectionDAG node without adding a corresponding IR intrinsic.  See ISD::FIRST_TARGET_MEMORY_OPCODE.


(Sorry, just noticed I had an unsubmitted comment here).

I think in this case I do need an intrinsic, as I want mask calculation and so on to be produced as early as possible (i.e. in IR with the help of AtomicExpandPass), and then want to pass this through to my target pseudo-instruction. The only way of doing so is via an intrinsic. If the mask generation were taking place when creating or transforming the SelectionDAG it seems `ISD::FIRST_TARGET_MEMORY_OPCODE` would be the best approach.


https://reviews.llvm.org/D48131