[PATCH] D52072: [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1

[Zixuan Wu via Phabricator via llvm-commits]

wuzish updated this revision to Diff 165466.
wuzish added a comment.

Add some comments in test cases.


https://reviews.llvm.org/D52072

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/crash.ll


Index: llvm/test/CodeGen/PowerPC/crash.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/crash.ll
+++ llvm/test/CodeGen/PowerPC/crash.ll
@@ -15,3 +15,20 @@
   store i8 %bf.set, i8* %x3, align 4
   ret void
 }
+
+; A BUILD_VECTOR of 1 element caused a crash in combineBVOfConsecutiveLoads()
+; Test that this is no longer the case
+define signext i32 @test2() {
+entry:
+  %retval = alloca i32, align 4
+  %__a = alloca i128, align 16
+  %b = alloca i64, align 8
+  store i32 0, i32* %retval, align 4
+  %0 = load i128, i128* %__a, align 16
+  %splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0
+  %splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitializer
+  %1 = bitcast <1 x i128> %splat.splat to <2 x i64>
+  %2 = extractelement <2 x i64> %1, i32 0
+  store i64 %2, i64* %b, align 8
+  ret i32 0
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11890,7 +11890,8 @@
     IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
   }
   // Not a build vector of (possibly fp_rounded) loads.
-  if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD)
+  if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) ||
+      N->getNumOperands() == 1)
     return SDValue();
 
   for (int i = 1, e = N->getNumOperands(); i < e; ++i) {


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