[PATCH] D52040: [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8

[Jinsong Ji via Phabricator via llvm-commits]

jsji created this revision.
jsji added reviewers: hfinkel, nemanjai, stefanp.
Herald added a subscriber: hiraditya.

When doing some instruction scheduling work, we noticed some missing itineraries.

Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, 
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, 
then causing different scheduling or suboptimal scheduling further.

This patch is for IIC_IntMulHD, and we add a new testcase in https://reviews.llvm.org/D52039 to show the difference.


Repository:
  rL LLVM

https://reviews.llvm.org/D52040

Files:
  llvm/lib/Target/PowerPC/PPCScheduleP7.td
  llvm/lib/Target/PowerPC/PPCScheduleP8.td
  llvm/test/CodeGen/PowerPC/mulld.ll


Index: llvm/test/CodeGen/PowerPC/mulld.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/mulld.ll
+++ llvm/test/CodeGen/PowerPC/mulld.ll
@@ -18,10 +18,10 @@
 
 ; CHECK-ITIN-LABEL: bn_mul_comba8:
 ; CHECK-ITIN:    mulhdu
-; CHECK-ITIN-NEXT:    mulhdu
 ; CHECK-ITIN-NEXT:    mulld
 ; CHECK-ITIN-NEXT:    mulhdu
 ; CHECK-ITIN-NEXT:    mulld
+; CHECK-ITIN-NEXT:    mulhdu
 
   %1 = load i64, i64* %a, align 8
   %conv = zext i64 %1 to i128
Index: llvm/lib/Target/PowerPC/PPCScheduleP8.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCScheduleP8.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP8.td
@@ -90,6 +90,10 @@
                                                   P8_DU4, P8_DU5, P8_DU6], 0>,
                                    InstrStage<1, [P8_FXU1, P8_FXU2]>],
                                   [4, 1, 1]>,
+  InstrItinData<IIC_IntMulHD    , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
+                                                  P8_DU4, P8_DU5, P8_DU6], 0>,
+                                   InstrStage<1, [P8_FXU1, P8_FXU2]>],
+                                  [4, 1, 1]>,
   InstrItinData<IIC_IntMulLI    , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
                                                   P8_DU4, P8_DU5, P8_DU6], 0>,
                                    InstrStage<1, [P8_FXU1, P8_FXU2]>],
Index: llvm/lib/Target/PowerPC/PPCScheduleP7.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCScheduleP7.td
+++ llvm/lib/Target/PowerPC/PPCScheduleP7.td
@@ -114,6 +114,10 @@
                                                   P7_DU3, P7_DU4], 0>,
                                    InstrStage<1, [P7_FX1, P7_FX2]>],
                                   [4, 1, 1]>,
+  InstrItinData<IIC_IntMulHD    , [InstrStage<1, [P7_DU1, P7_DU2,
+                                                  P7_DU3, P7_DU4], 0>,
+                                   InstrStage<1, [P7_FX1, P7_FX2]>],
+                                  [4, 1, 1]>,
   InstrItinData<IIC_IntMulLI    , [InstrStage<1, [P7_DU1, P7_DU2,
                                                   P7_DU3, P7_DU4], 0>,
                                    InstrStage<1, [P7_FX1, P7_FX2]>],


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