[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

[Matt Arsenault via Phabricator via llvm-commits]

arsenm requested changes to this revision.
arsenm added inline comments.
This revision now requires changes to proceed.


================
Comment at: lib/Target/AMDGPU/Utils/AMDGPUMCUtils.cpp:23-25
+Optional<int64_t> foldToImm(const MachineOperand &Op,
+                            const MachineRegisterInfo *MRI, const SIInstrInfo *TII) {
+  if (Op.isImm()) {
----------------
This seems more like something for TII


Repository:
  rL LLVM

https://reviews.llvm.org/D51932