[PATCH] D51518: [WebAssembly] Add missing SIMD instruction attributes

[Thomas Lively via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL342104: [WebAssembly] Add missing SIMD instruction attributes (authored by tlively, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D51518?vs=165188&id=165196#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51518

Files:
  llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td


Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -19,21 +19,22 @@
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
 multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
+  let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in
   defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
                                   [(set V128:$dst, (vec_t pat))],
                                   "v128.const\t$dst, "#args,
                                   "v128.const\t"#args, 0>;
 }
 multiclass SIMDLoad<ValueType vec_t> {
-  let mayLoad = 1 in
+  let mayLoad = 1, isAsCheapAsAMove = 1 in
   defm LOAD_#vec_t :
     SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$align, offset32_op:$off), [],
            "v128.load\t$dst, ${off}(${addr})$align",
            "v128.load\t$off$align", 1>;
 }
 multiclass SIMDStore<ValueType vec_t> {
-  let mayStore = 1 in
+  let mayStore = 1, isAsCheapAsAMove = 1 in
   defm STORE_#vec_t :
     SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
            (outs), (ins P2Align:$align, offset32_op:$off), [],


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