[llvm] r342030 - [AArch64] Add parsing of aarch64_vector_pcs attribute.
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 12 01:54:07 PDT 2018
Author: s.desmalen
Date: Wed Sep 12 01:54:06 2018
New Revision: 342030
URL: http://llvm.org/viewvc/llvm-project?rev=342030&view=rev
Log:
[AArch64] Add parsing of aarch64_vector_pcs attribute.
This patch adds parsing support for the 'aarch64_vector_pcs'
calling convention attribute to calls and function declarations.
More information describing the vector ABI and procedure call standard
can be found here:
https://developer.arm.com/products/software-development-tools/\
hpc/arm-compiler-for-hpc/vector-function-abi
Reviewers: t.p.northover, rnk, rengolin, javed.absar, thegameg, SjoerdMeijer
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D51477
Added:
llvm/trunk/test/Bitcode/vector-pcs.ll
Modified:
llvm/trunk/include/llvm/IR/CallingConv.h
llvm/trunk/lib/AsmParser/LLLexer.cpp
llvm/trunk/lib/AsmParser/LLParser.cpp
llvm/trunk/lib/AsmParser/LLToken.h
llvm/trunk/lib/IR/AsmWriter.cpp
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
Modified: llvm/trunk/include/llvm/IR/CallingConv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/CallingConv.h?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/CallingConv.h (original)
+++ llvm/trunk/include/llvm/IR/CallingConv.h Wed Sep 12 01:54:06 2018
@@ -220,6 +220,9 @@ namespace CallingConv {
/// shader if tessellation is in use, or otherwise the vertex shader.
AMDGPU_ES = 96,
+ // Calling convention between AArch64 Advanced SIMD functions
+ AArch64_VectorCall = 97,
+
/// The highest possible calling convention ID. Must be some 2^k - 1.
MaxID = 1023
};
Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLLexer.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLLexer.cpp Wed Sep 12 01:54:06 2018
@@ -592,6 +592,7 @@ lltok::Kind LLLexer::LexIdentifier() {
KEYWORD(arm_apcscc);
KEYWORD(arm_aapcscc);
KEYWORD(arm_aapcs_vfpcc);
+ KEYWORD(aarch64_vector_pcs);
KEYWORD(msp430_intrcc);
KEYWORD(avr_intrcc);
KEYWORD(avr_signalcc);
Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Sep 12 01:54:06 2018
@@ -1874,6 +1874,7 @@ void LLParser::ParseOptionalDLLStorageCl
/// ::= 'arm_apcscc'
/// ::= 'arm_aapcscc'
/// ::= 'arm_aapcs_vfpcc'
+/// ::= 'aarch64_vector_pcs'
/// ::= 'msp430_intrcc'
/// ::= 'avr_intrcc'
/// ::= 'avr_signalcc'
@@ -1917,6 +1918,7 @@ bool LLParser::ParseOptionalCallingConv(
case lltok::kw_arm_apcscc: CC = CallingConv::ARM_APCS; break;
case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;
+ case lltok::kw_aarch64_vector_pcs:CC = CallingConv::AArch64_VectorCall; break;
case lltok::kw_msp430_intrcc: CC = CallingConv::MSP430_INTR; break;
case lltok::kw_avr_intrcc: CC = CallingConv::AVR_INTR; break;
case lltok::kw_avr_signalcc: CC = CallingConv::AVR_SIGNAL; break;
Modified: llvm/trunk/lib/AsmParser/LLToken.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLToken.h?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLToken.h (original)
+++ llvm/trunk/lib/AsmParser/LLToken.h Wed Sep 12 01:54:06 2018
@@ -139,6 +139,7 @@ enum Kind {
kw_arm_apcscc,
kw_arm_aapcscc,
kw_arm_aapcs_vfpcc,
+ kw_aarch64_vector_pcs,
kw_msp430_intrcc,
kw_avr_intrcc,
kw_avr_signalcc,
Modified: llvm/trunk/lib/IR/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/AsmWriter.cpp?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/lib/IR/AsmWriter.cpp (original)
+++ llvm/trunk/lib/IR/AsmWriter.cpp Wed Sep 12 01:54:06 2018
@@ -363,6 +363,7 @@ static void PrintCallingConv(unsigned cc
case CallingConv::ARM_APCS: Out << "arm_apcscc"; break;
case CallingConv::ARM_AAPCS: Out << "arm_aapcscc"; break;
case CallingConv::ARM_AAPCS_VFP: Out << "arm_aapcs_vfpcc"; break;
+ case CallingConv::AArch64_VectorCall: Out << "aarch64_vector_pcs"; break;
case CallingConv::MSP430_INTR: Out << "msp430_intrcc"; break;
case CallingConv::AVR_INTR: Out << "avr_intrcc "; break;
case CallingConv::AVR_SIGNAL: Out << "avr_signalcc "; break;
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Sep 12 01:54:06 2018
@@ -2896,6 +2896,8 @@ CCAssignFn *AArch64TargetLowering::CCAss
return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
case CallingConv::Win64:
return IsVarArg ? CC_AArch64_Win64_VarArg : CC_AArch64_AAPCS;
+ case CallingConv::AArch64_VectorCall:
+ return CC_AArch64_AAPCS;
}
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp?rev=342030&r1=342029&r2=342030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.cpp Wed Sep 12 01:54:06 2018
@@ -49,6 +49,9 @@ AArch64RegisterInfo::getCalleeSavedRegs(
return CSR_AArch64_NoRegs_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
return CSR_AArch64_AllRegs_SaveList;
+ if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall)
+ // FIXME: default to AAPCS until we add full support.
+ return CSR_AArch64_AAPCS_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
@@ -98,6 +101,9 @@ AArch64RegisterInfo::getCallPreservedMas
if (CC == CallingConv::CXX_FAST_TLS)
return SCS ? CSR_AArch64_CXX_TLS_Darwin_SCS_RegMask
: CSR_AArch64_CXX_TLS_Darwin_RegMask;
+ if (CC == CallingConv::AArch64_VectorCall)
+ // FIXME: default to AAPCS until we add full support.
+ return SCS ? CSR_AArch64_AAPCS_SCS_RegMask : CSR_AArch64_AAPCS_RegMask;
if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
->supportSwiftError() &&
MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
Added: llvm/trunk/test/Bitcode/vector-pcs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Bitcode/vector-pcs.ll?rev=342030&view=auto
==============================================================================
--- llvm/trunk/test/Bitcode/vector-pcs.ll (added)
+++ llvm/trunk/test/Bitcode/vector-pcs.ll Wed Sep 12 01:54:06 2018
@@ -0,0 +1,11 @@
+; RUN: llvm-as %s -o - -f | llvm-dis | FileCheck %s
+; RUN: llvm-as %s -o - -f | verify-uselistorder
+
+declare aarch64_vector_pcs void @aarch64_vector_pcs()
+; CHECK: declare aarch64_vector_pcs void @aarch64_vector_pcs
+
+define void @call_aarch64_vector_pcs() {
+; CHECK: call aarch64_vector_pcs void @aarch64_vector_pcs
+ call aarch64_vector_pcs void @aarch64_vector_pcs()
+ ret void
+}
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