[llvm] r341919 - [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction

[Hans Wennborg via llvm-commits]

It's pretty late, and unless any serious bug shows up the plan is not
to do any more release candidates.

I'll put this on my list in case we do another release candidate for
some other reason, but otherwise I'd prefer not to merge it.

Thanks,
Hans

On Tue, Sep 11, 2018 at 4:09 PM, Simon Atanasyan via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Hi,
>
> If it's not too late, could r341919 revision be merged into the
> release_70 branch? The fix is local and affects MIPS code only.
>
> Thanks in advance.
>
> On Tue, Sep 11, 2018 at 12:58 PM Simon Atanasyan via llvm-commits
> <llvm-commits at lists.llvm.org> wrote:
>>
>> Author: atanasyan
>> Date: Tue Sep 11 02:57:25 2018
>> New Revision: 341919
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=341919&view=rev
>> Log:
>> [mips] Add a pattern for 64-bit GPR variant of the `rdhwr` instruction
>>
>> MIPS ISAs start to support third operand for the `rdhwr` instruction
>> starting from Revision 6. But LLVM generates assembler code with
>> three-operands version of this instruction on any MIPS64 ISA. The third
>> operand is always zero, so in case of direct code generation we get
>> correct code.
>>
>> This patch fixes the bug by adding an instruction alias. The same alias
>> already exists for 32-bit ISA.
>>
>> Ideally, we also need to reject three-operands version of the `rdhwr`
>> instruction in an assembler code if ISA revision is less than 6. That is
>> a task for a separate patch.
>>
>> This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861)
>>
>> Differential revision: https://reviews.llvm.org/D51773
>>
>> Modified:
>>     llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
>>     llvm/trunk/test/CodeGen/Mips/tls.ll
>>
>> Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=341919&r1=341918&r2=341919&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
>> +++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Tue Sep 11 02:57:25 2018
>> @@ -1139,3 +1139,6 @@ def SLTUImm64 : MipsAsmPseudoInst<(outs
>>                                    "sltu\t$rs, $rt, $imm">, GPR_64;
>>  def : MipsInstAlias<"sltu\t$rs, $imm", (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs,
>>                                                    imm64:$imm)>, GPR_64;
>> +
>> +def : MipsInstAlias<"rdhwr $rt, $rs",
>> +                    (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64;
>>
>> Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=341919&r1=341918&r2=341919&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
>> +++ llvm/trunk/test/CodeGen/Mips/tls.ll Tue Sep 11 02:57:25 2018
>> @@ -48,14 +48,14 @@ entry:
>>  ; STATIC32-LABEL:   f1:
>>  ; STATIC32:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
>>  ; STATIC32:   addiu   $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
>> -; STATIC32:   rdhwr   $3, $29
>> +; STATIC32:   rdhwr   $3, $29{{$}}
>>  ; STATIC32:   addu    $[[R2:[0-9]+]], $3, $[[R1]]
>>  ; STATIC32:   lw      $2, 0($[[R2]])
>>
>>  ; STATIC64-LABEL:   f1:
>>  ; STATIC64:   lui     $[[R0:[0-9]+]], %tprel_hi(t1)
>>  ; STATIC64:   daddiu  $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
>> -; STATIC64:   rdhwr   $3, $29, 0
>> +; STATIC64:   rdhwr   $3, $29{{$}}
>>  ; STATIC64:   daddu   $[[R2:[0-9]+]], $3, $[[R0]]
>>  ; STATIC64:   lw      $2, 0($[[R2]])
>>  }
>> @@ -101,7 +101,7 @@ entry:
>>  ; STATIC32-LABEL:   f2:
>>  ; STATIC32:   lui     $[[R0:[0-9]+]], %hi(__gnu_local_gp)
>>  ; STATIC32:   addiu   $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
>> -; STATIC32:   rdhwr   $3, $29
>> +; STATIC32:   rdhwr   $3, $29{{$}}
>>  ; STATIC32:   lw      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
>>  ; STATIC32:   addu    $[[R1:[0-9]+]], $3, $[[R0]]
>>  ; STATIC32:   lw      $2, 0($[[R1]])
>> @@ -109,7 +109,7 @@ entry:
>>  ; STATIC64-LABEL:   f2:
>>  ; STATIC64:   lui     $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
>>  ; STATIC64:   daddiu  $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
>> -; STATIC64:   rdhwr   $3, $29
>> +; STATIC64:   rdhwr   $3, $29{{$}}
>>  ; STATIC64:   ld      $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
>>  ; STATIC64:   daddu   $[[R1:[0-9]+]], $3, $[[R0]]
>>  ; STATIC64:   lw      $2, 0($[[R1]])
>
> --
> Simon Atanasyan
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