[PATCH] D51696: [SelectionDAG] enhance vector demanded elements to look at a vector select condition operand

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/TargetLowering.cpp:1539
+    // TODO - add support for constant vselect masks (see IR version of this).
+    APInt UnusedUndef, UnusedZero;
+    if (SimplifyDemandedVectorElts(Op.getOperand(0), DemandedElts, UnusedUndef,
----------------
spatel wrote:
> RKSimon wrote:
> > Can we use UnusedZero to alter the LHS/RHS DemandedElts ?
> If UnusedZero (if we do use it, I'll change the name of course) has set bits, that would mean that we're choosing RHS elements in this select, right?
> 
> UnusedUndef is probably the more interesting part, and that's what the TODO comment is alluding to. I'm not sure what we decided on this: if an element of the condition is undef, does that mean the result is undef? In that case, I think we could do something like this below here:
> KnownUndef = UndefCond | (UndefLHS & UndefRHS);
> 
> I did try that change, but there were no existing test diffs, so I thought it was better left for a follow-up.
> If UnusedZero (if we do use it, I'll change the name of course) has set bits, that would mean that we're choosing RHS elements in this select, right?

Yes, Known zero select values demand RHS and ignore LHS - remember that the unknown/zero masks are only guaranteed to be correct for demanded elements.

> KnownUndef = UndefCond | (UndefLHS & UndefRHS);

I think the only case we can UndefCond is if UndefLHS & UndefRHS are both known to be true, something like:

KnownUndef = (SelectLHS & UndefLHS) | (SelectRHS & UndefRHS);
KnownUndef |= UndefCond & (UndefLHS & UndefRHS);



https://reviews.llvm.org/D51696