[llvm] r341512 - [X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed Sep  5 19:03:14 2018
New Revision: 341512

URL: http://llvm.org/viewvc/llvm-project?rev=341512&view=rev
Log:
[X86][Assembler] Allow %eip as a register in 32-bit mode for .cfi directives.

This basically reverts a change made in r336217, but improves the text of the error message for not allowing IP-relative addressing in 32-bit mode.

Fixes PR38826.

Patch by Iain Sandoe.

Added:
    llvm/trunk/test/MC/X86/pr38826.s
Modified:
    llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/trunk/test/CodeGen/X86/eip-addressing-i386.ll
    llvm/trunk/test/MC/X86/x86_errors.s

Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=341512&r1=341511&r2=341512&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Wed Sep  5 19:03:14 2018
@@ -1054,7 +1054,7 @@ static bool CheckBaseRegAndIndexRegAndSc
   // RIP/EIP-relative addressing is only supported in 64-bit mode.
   if (!Is64BitMode && BaseReg != 0 &&
       (BaseReg == X86::RIP || BaseReg == X86::EIP)) {
-    ErrMsg = "RIP-relative addressing requires 64-bit mode";
+    ErrMsg = "IP-relative addressing requires 64-bit mode";
     return true;
   }
 
@@ -1099,7 +1099,7 @@ bool X86AsmParser::ParseRegister(unsigne
     // checked.
     // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
     // REX prefix.
-    if (RegNo == X86::RIZ || RegNo == X86::RIP || RegNo == X86::EIP ||
+    if (RegNo == X86::RIZ || RegNo == X86::RIP ||
         X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
         X86II::isX86_64NonExtLowByteReg(RegNo) ||
         X86II::isX86_64ExtendedReg(RegNo))

Modified: llvm/trunk/test/CodeGen/X86/eip-addressing-i386.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/eip-addressing-i386.ll?rev=341512&r1=341511&r2=341512&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/eip-addressing-i386.ll (original)
+++ llvm/trunk/test/CodeGen/X86/eip-addressing-i386.ll Wed Sep  5 19:03:14 2018
@@ -1,8 +1,8 @@
 ; RUN: not llc -mtriple i386-apple-- -o /dev/null < %s 2>&1| FileCheck %s
-; CHECK: <inline asm>:1:13: error: register %eip is only available in 64-bit mode
+; CHECK: <inline asm>:1:13: error: IP-relative addressing requires 64-bit mode
 ; CHECK-NEXT: jmpl *_foo(%eip)
 
-; Make sure that we emit an error if we encounter RIP-relative instructions in
+; Make sure that we emit an error if we encounter IP-relative instructions in
 ; 32-bit mode.
 
 define i32 @foo() { ret i32 0 }

Added: llvm/trunk/test/MC/X86/pr38826.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/pr38826.s?rev=341512&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/pr38826.s (added)
+++ llvm/trunk/test/MC/X86/pr38826.s Wed Sep  5 19:03:14 2018
@@ -0,0 +1,24 @@
+// RUN: llvm-mc %s -triple i386-unknown-unknown
+
+// Make sure %eip is allowed as a register in cfi directives in 32-bit mode
+
+ .text
+ .align 4
+ .globl foo
+
+foo:
+ .cfi_startproc
+
+ movl (%edx), %ecx
+ movl 4(%edx), %ebx
+ movl 8(%edx), %esi
+ movl 12(%edx), %edi
+ movl 16(%edx), %ebp
+ .cfi_def_cfa %edx, 0
+ .cfi_offset %eip, 24
+ .cfi_register %esp, %ecx
+ movl %ecx, %esp
+
+ jmp *24(%edx)
+
+ .cfi_endproc

Modified: llvm/trunk/test/MC/X86/x86_errors.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_errors.s?rev=341512&r1=341511&r2=341512&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_errors.s (original)
+++ llvm/trunk/test/MC/X86/x86_errors.s Wed Sep  5 19:03:14 2018
@@ -103,11 +103,11 @@ lea (%si,%bx), %ax
 // 64: error: invalid 16-bit base register
 lea (%di,%bx), %ax
 
-// 32: error: register %eip is only available in 64-bit mode
+// 32: error: invalid base+index expression
 // 64: error: invalid base+index expression
 mov (,%eip), %rbx
 
-// 32: error: register %eip is only available in 64-bit mode
+// 32: error: invalid base+index expression
 // 64: error: invalid base+index expression
 mov (%eip,%eax), %rbx