[PATCH] D48580: [AArch64] Support reserving x1-7 registers.

[Tri Vo via Phabricator via llvm-commits]

trong marked 3 inline comments as done.
trong added inline comments.


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Comment at: lib/Target/AArch64/AArch64RegisterInfo.cpp:452-454
+    for (size_t i = 0; i < AArch64::GPR64commonRegClass.getNumRegs(); ++i) {
+      if (MF.getSubtarget<AArch64Subtarget>().isXRegisterReserved(i)) ++NumReserved;
+    }
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nickdesaulniers wrote:
> std::count()
Using BitVector::count() since we already have a BitVector.


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Comment at: lib/Target/AArch64/AArch64Subtarget.cpp:155
     : AArch64GenSubtargetInfo(TT, CPU, FS),
-      ReserveX18(AArch64::isX18ReservedByDefault(TT)), IsLittle(LittleEndian),
+      ReserveXRegister(31), IsLittle(LittleEndian),
       TargetTriple(TT), FrameLowering(),
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nickdesaulniers wrote:
> Sorry, where does `31` come from here?
Changed this to use tablegen generated value.


https://reviews.llvm.org/D48580