[llvm] r341411 - [WebAssembly][NFC] Fix formatting and tests

[Thomas Lively via llvm-commits]

Author: tlively
Date: Tue Sep  4 14:26:17 2018
New Revision: 341411

URL: http://llvm.org/viewvc/llvm-project?rev=341411&view=rev
Log:
[WebAssembly][NFC] Fix formatting and tests

Summary: Small fixes

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51656

Modified:
    llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
    llvm/trunk/test/CodeGen/WebAssembly/simd.ll

Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=341411&r1=341410&r2=341411&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Tue Sep  4 14:26:17 2018
@@ -71,7 +71,7 @@ multiclass ExtractPat<ValueType lane_t,
 defm extract_i8x16 : ExtractPat<i8, 0xff>;
 defm extract_i16x8 : ExtractPat<i16, 0xffff>;
 multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
-  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32,  baseInst, sign,
+  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
                         !cast<PatFrag>("extract_i8x16"#sign)>;
   defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 2), sign,
                         !cast<PatFrag>("extract_i16x8"#sign)>;

Modified: llvm/trunk/test/CodeGen/WebAssembly/simd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd.ll?rev=341411&r1=341410&r2=341411&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd.ll Tue Sep  4 14:26:17 2018
@@ -37,7 +37,7 @@ define <16 x i8> @splat_v16i8(i8 %x) {
   ret <16 x i8> %res
 }
 
-; CHECK-LABEL: const_splat_v16i8
+; CHECK-LABEL: const_splat_v16i8:
 ; SIMD128; i8x16.splat
 define <16 x i8> @const_splat_v16i8() {
   ret <16 x i8> <i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
@@ -267,7 +267,7 @@ define <4 x i32> @splat_v4i32(i32 %x) {
   ret <4 x i32> %res
 }
 
-; CHECK-LABEL: const_splat_v4i32
+; CHECK-LABEL: const_splat_v4i32:
 ; SIMD128; i32x4.splat
 define <4 x i32> @const_splat_v4i32() {
   ret <4 x i32> <i32 42, i32 42, i32 42, i32 42>
@@ -340,6 +340,12 @@ define <2 x i64> @splat_v2i64(i64 %x) {
   ret <2 x i64> %res
 }
 
+; CHECK-LABEL: const_splat_v2i64:
+; SIMD128; i64x2.splat
+define <2 x i64> @const_splat_v2i64() {
+  ret <2 x i64> <i64 42, i64 42>
+}
+
 ; CHECK-LABEL: extract_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2
@@ -364,10 +370,6 @@ define <2 x i64> @replace_v2i64(<2 x i64
   ret <2 x i64> %res
 }
 
-define <2 x i64> @const_splat_v2i64() {
-  ret <2 x i64> <i64 42, i64 42>
-}
-
 ; CHECK-LABEL: build_v2i64:
 ; NO-SIMD128-NOT: i64x2
 ; SIMD128-VM-NOT: i64x2