[llvm] r341317 - DAG: Handle extract_vector_elt in isKnownNeverNaN

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Sep  3 07:01:03 2018
New Revision: 341317

URL: http://llvm.org/viewvc/llvm-project?rev=341317&view=rev
Log:
DAG: Handle extract_vector_elt in isKnownNeverNaN

Added:
    llvm/trunk/test/CodeGen/AMDGPU/known-never-nan.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=341317&r1=341316&r2=341317&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Sep  3 07:01:03 2018
@@ -3715,6 +3715,9 @@ bool SelectionDAG::isKnownNeverNaN(SDVal
 
   // TODO: Handle FMINNUM/FMAXNUM/FMINNAN/FMAXNAN when there is an agreement on
   // what they should do.
+  case ISD::EXTRACT_VECTOR_ELT: {
+    return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
+  }
   default:
     if (Opcode >= ISD::BUILTIN_OP_END ||
         Opcode == ISD::INTRINSIC_WO_CHAIN ||

Added: llvm/trunk/test/CodeGen/AMDGPU/known-never-nan.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/known-never-nan.ll?rev=341317&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/known-never-nan.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/known-never-nan.ll Mon Sep  3 07:01:03 2018
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+
+define half @known_nnan_extract_vector_elt(float %a, float %b, i32 %idx, half %c) {
+; GCN-LABEL: known_nnan_extract_vector_elt:
+; GCN:       ; %bb.0:
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cvt_pkrtz_f16_f32 v0, v0, v1
+; GCN-NEXT:    v_lshlrev_b32_e32 v1, 4, v2
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
+; GCN-NEXT:    v_add_f16_e32 v1, 1.0, v3
+; GCN-NEXT:    v_cmp_lt_f16_e32 vcc, v0, v1
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; GCN-NEXT:    s_setpc_b64 s[30:31]
+  %cvt = call nnan <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b)
+  %extract = extractelement <2 x half> %cvt, i32 %idx
+  %canon = call half @llvm.canonicalize.f16(half %extract)
+  %nnan.c = fadd nnan nsz half %c, 1.0
+  %cmp = fcmp olt half %extract, %nnan.c
+  %select = select i1 %cmp, half %extract, half %nnan.c
+  ret half %select
+}
+
+declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0
+declare half @llvm.canonicalize.f16(half) #0