[PATCH] D51570: [X86][XOP] VFRCZ* instructions should be in their own sched class

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

I think you'd be much better off just adding InstRW overrides to your prototype model, similar to how SSE4A instructions are handled in the btver2/znver1 models. Once we have actual models in trunk that support these instructions we can revisit this if you have a strong use case.



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Comment at: lib/Target/X86/X86SchedSandyBridge.td:15
 // but we still have to define them because SNB is the default subtarget for
 // X86. These instructions are tagged with a comment `Unsupported = 1`.
 //
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This comment explains that SNB must support all models as its used as the generic model.


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Comment at: test/tools/llvm-mca/X86/Generic/resources-xop.s:2
+# It seems we can't actually run this test using generic cpu, since these are XOP instructions, and the generic cpu does not support them.
+# -R-U-N-: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
+
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You are missing the whole point of the generic model by doing this.


Repository:
  rL LLVM

https://reviews.llvm.org/D51570