[llvm] r341278 - [AVR] Redefine the 'LSL' instruction as an alias of 'ADD'
Dylan McKay via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 1 05:23:00 PDT 2018
Author: dylanmckay
Date: Sat Sep 1 05:23:00 2018
New Revision: 341278
URL: http://llvm.org/viewvc/llvm-project?rev=341278&view=rev
Log:
[AVR] Redefine the 'LSL' instruction as an alias of 'ADD'
The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'.
Modified:
llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp
llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
Modified: llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp?rev=341278&r1=341277&r2=341278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRExpandPseudoInsts.cpp Sat Sep 1 05:23:00 2018
@@ -1251,13 +1251,14 @@ bool AVRExpandPseudo::expand<AVR::LSLWRd
bool DstIsDead = MI.getOperand(0).isDead();
bool DstIsKill = MI.getOperand(1).isKill();
bool ImpIsDead = MI.getOperand(2).isDead();
- OpLo = AVR::LSLRd;
+ OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
TRI->splitReg(DstReg, DstLoReg, DstHiReg);
// Low part
buildMI(MBB, MBBI, OpLo)
.addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+ .addReg(DstLoReg)
.addReg(DstLoReg, getKillRegState(DstIsKill));
auto MIBHI = buildMI(MBB, MBBI, OpHi)
@@ -1388,8 +1389,9 @@ template <> bool AVRExpandPseudo::expand
.addReg(SrcReg, getKillRegState(SrcIsKill));
}
- buildMI(MBB, MBBI, AVR::LSLRd)
+ buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
.addReg(DstHiReg, RegState::Define)
+ .addReg(DstHiReg)
.addReg(DstHiReg, RegState::Kill);
auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
Modified: llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp?rev=341278&r1=341277&r2=341278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRISelLowering.cpp Sat Sep 1 05:23:00 2018
@@ -1441,8 +1441,9 @@ MachineBasicBlock *AVRTargetLowering::in
default:
llvm_unreachable("Invalid shift opcode!");
case AVR::Lsl8:
- Opc = AVR::LSLRd;
+ Opc = AVR::ADDRdRr; // LSL is an alias of ADD Rd, Rd
RC = &AVR::GPR8RegClass;
+ HasRepeatedOperand = true;
break;
case AVR::Lsl16:
Opc = AVR::LSLWRd;
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.td?rev=341278&r1=341277&r2=341278&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.td Sat Sep 1 05:23:00 2018
@@ -1632,12 +1632,7 @@ def LATZRd : FZRd<0b111,
let Constraints = "$src = $rd",
Defs = [SREG] in
{
- def LSLRd : FRdRr<0b0000,
- 0b11,
- (outs GPR8:$rd),
- (ins GPR8:$src),
- "lsl\t$rd",
- [(set i8:$rd, (AVRlsl i8:$src)), (implicit SREG)]>;
+ // 8-bit LSL is an alias of ADD Rd, Rd
def LSLWRd : Pseudo<(outs DREGS:$rd),
(ins DREGS:$src),
@@ -1755,6 +1750,12 @@ Defs = [SREG] in
// Clears all bits in a register.
def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8:$rd, GPR8:$rd)>;
+// LSL Rd
+// Alias for ADD Rd, Rd
+// --------------
+// Logical shift left one bit.
+def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8:$rd, GPR8:$rd)>;
+
def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8:$rd, GPR8:$rd)>;
// SER Rd
@@ -2098,5 +2099,10 @@ def : Pat<(shl i16:$src1, (i8 1)),
// Lowering of 'tst' node to 'TST' instruction.
// TST is an alias of AND Rd, Rd.
def : Pat<(AVRtst i8:$rd),
- (ANDRdRr $rd, $rd)>;
+ (ANDRdRr GPR8:$rd, GPR8:$rd)>;
+
+// Lowering of 'lsl' node to 'LSL' instruction.
+// LSL is an alias of 'ADD Rd, Rd'
+def : Pat<(AVRlsl i8:$rd),
+ (ADDRdRr GPR8:$rd, GPR8:$rd)>;
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir?rev=341278&r1=341277&r2=341278&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/LSLWRd.mir Sat Sep 1 05:23:00 2018
@@ -15,7 +15,7 @@ body: |
; CHECK-LABEL: test
- ; CHECK: $r14 = LSLRd $r14, implicit-def $sreg
+ ; CHECK: $r14 = ADDRdRr $r14, $r14, implicit-def $sreg
; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
$r15r14 = LSLWRd $r15r14, implicit-def $sreg
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir?rev=341278&r1=341277&r2=341278&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/SEXT.mir Sat Sep 1 05:23:00 2018
@@ -17,7 +17,7 @@ body: |
; CHECK: $r14 = MOVRdRr $r31
; CHECK-NEXT: $r15 = MOVRdRr $r31
- ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
$r15r14 = SEXT $r31, implicit-def $sreg
Modified: llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir?rev=341278&r1=341277&r2=341278&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir (original)
+++ llvm/trunk/test/CodeGen/AVR/pseudo/ZEXT.mir Sat Sep 1 05:23:00 2018
@@ -17,7 +17,7 @@ body: |
; CHECK: $r14 = MOVRdRr $r31
; CHECK-NEXT: $r15 = MOVRdRr $r31
- ; CHECK-NEXT: $r15 = LSLRd killed $r15, implicit-def $sreg
+ ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
$r15r14 = SEXT $r31, implicit-def $sreg
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