[PATCH] D51534: [X86][BtVer2] Remove wrong ReadAdvance from AVX vbroadcast(ss|sd|F128) instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, craig.topper, spatel, lebedev.ri.
Herald added a subscriber: gbedwell.

The presence of a ReadAdvance for the input operand at index 0 is problematic (as shown by the diff in the llvm-mca test).
A broadcast cannot start executing if the base address for the load hasn't been computed yet.

In the llvm-mca example, the VBROADCASTSS has to wait on the write from LEAQ. If we apply ReadAdvance to the register read associated with the base address, then we wrongly assume that the load can start 3 cycles in advance.


https://reviews.llvm.org/D51534

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/vbroadcast-operand-latency.s


Index: test/tools/llvm-mca/X86/BtVer2/vbroadcast-operand-latency.s
===================================================================
--- test/tools/llvm-mca/X86/BtVer2/vbroadcast-operand-latency.s
+++ test/tools/llvm-mca/X86/BtVer2/vbroadcast-operand-latency.s
@@ -6,7 +6,7 @@
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      200
-# CHECK-NEXT: Total Cycles:      208
+# CHECK-NEXT: Total Cycles:      209
 # CHECK-NEXT: Total uOps:        300
 
 # CHECK:      Dispatch Width:    2
@@ -52,22 +52,22 @@
 # CHECK-NEXT:  -      -      -     2.00   2.00   1.00   1.00   1.00    -      -      -      -      -      -     vbroadcastss	(%rax), %ymm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123
+# CHECK-NEXT:                     01234
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    .  .   leaq	8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: [0,1]     .DeeeeeeER.  .   vbroadcastss	(%rax), %ymm0
-# CHECK-NEXT: [1,0]     . DeeE---R.  .   leaq	8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: [1,1]     .  DeeeeeeER .   vbroadcastss	(%rax), %ymm0
-# CHECK-NEXT: [2,0]     .   DeeE---R .   leaq	8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: [2,1]     .    DeeeeeeER   vbroadcastss	(%rax), %ymm0
+# CHECK:      [0,0]     DeeER.    .   .   leaq	8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: [0,1]     .D=eeeeeeER   .   vbroadcastss	(%rax), %ymm0
+# CHECK-NEXT: [1,0]     . DeeE----R   .   leaq	8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: [1,1]     .  D=eeeeeeER .   vbroadcastss	(%rax), %ymm0
+# CHECK-NEXT: [2,0]     .   DeeE----R .   leaq	8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: [2,1]     .    D=eeeeeeER   vbroadcastss	(%rax), %ymm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     1.0    1.0    2.0       leaq	8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: 1.     3     1.0    1.0    0.0       vbroadcastss	(%rax), %ymm0
+# CHECK-NEXT: 0.     3     1.0    1.0    2.7       leaq	8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: 1.     3     2.0    0.0    0.0       vbroadcastss	(%rax), %ymm0
Index: lib/Target/X86/X86ScheduleBtVer2.td
===================================================================
--- lib/Target/X86/X86ScheduleBtVer2.td
+++ lib/Target/X86/X86ScheduleBtVer2.td
@@ -570,9 +570,9 @@
   let ResourceCycles = [1, 2, 4];
   let NumMicroOps = 2;
 }
-def : InstRW<[JWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm,
-                                                         VBROADCASTSSYrm,
-                                                         VBROADCASTF128)>;
+def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
+                                            VBROADCASTSSYrm,
+                                            VBROADCASTF128)>;
 
 def JWriteJVZEROALL: SchedWriteRes<[]> {
   let Latency = 90;


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