[llvm] r341128 - [WebAssembly] Vector conversions
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 30 14:43:51 PDT 2018
Author: tlively
Date: Thu Aug 30 14:43:51 2018
New Revision: 341128
URL: http://llvm.org/viewvc/llvm-project?rev=341128&view=rev
Log:
[WebAssembly] Vector conversions
Summary:
Lowers away bitconverts between vector types. This CL depends
on D51383.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D51498
Added:
llvm/trunk/test/CodeGen/WebAssembly/simd-conversions.ll
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=341128&r1=341127&r2=341128&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Thu Aug 30 14:43:51 2018
@@ -271,6 +271,17 @@ def : Pat<(i32 (vector_extract (v16i8 V1
def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
(EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
+// Bitcasts are nops
+// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
+foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
+foreach t2 = !foldl(
+ []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
+ acc, !listconcat(acc, [cur])
+ )
+) in
+def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
+
// arbitrary other BUILD_VECTOR patterns
def : Pat<(v16i8 (build_vector
(i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
Added: llvm/trunk/test/CodeGen/WebAssembly/simd-conversions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-conversions.ll?rev=341128&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-conversions.ll (added)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-conversions.ll Thu Aug 30 14:43:51 2018
@@ -0,0 +1,324 @@
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-keep-registers -wasm-disable-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
+
+; Test that bitcasts between vector types are lowered to zero instructions
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+; CHECK-LABEL: v16i8_to_v16i8:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <16 x i8> @v16i8_to_v16i8(<16 x i8> %v) {
+ %res = bitcast <16 x i8> %v to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v16i8_to_v8i16:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <8 x i16> @v16i8_to_v8i16(<16 x i8> %v) {
+ %res = bitcast <16 x i8> %v to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v16i8_to_v4i32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x i32> @v16i8_to_v4i32(<16 x i8> %v) {
+ %res = bitcast <16 x i8> %v to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v16i8_to_v2i64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x i64> @v16i8_to_v2i64(<16 x i8> %v) {
+ %res = bitcast <16 x i8> %v to <2 x i64>
+ ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v16i8_to_v4f32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x float> @v16i8_to_v4f32(<16 x i8> %v) {
+ %res = bitcast <16 x i8> %v to <4 x float>
+ ret <4 x float> %res
+}
+
+; CHECK-LABEL: v16i8_to_v2f64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x double> @v16i8_to_v2f64(<16 x i8> %v) {
+ %res = bitcast <16 x i8> %v to <2 x double>
+ ret <2 x double> %res
+}
+
+; CHECK-LABEL: v8i16_to_v16i8:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <16 x i8> @v8i16_to_v16i8(<8 x i16> %v) {
+ %res = bitcast <8 x i16> %v to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v8i16_to_v8i16:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <8 x i16> @v8i16_to_v8i16(<8 x i16> %v) {
+ %res = bitcast <8 x i16> %v to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v8i16_to_v4i32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x i32> @v8i16_to_v4i32(<8 x i16> %v) {
+ %res = bitcast <8 x i16> %v to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v8i16_to_v2i64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x i64> @v8i16_to_v2i64(<8 x i16> %v) {
+ %res = bitcast <8 x i16> %v to <2 x i64>
+ ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v8i16_to_v4f32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x float> @v8i16_to_v4f32(<8 x i16> %v) {
+ %res = bitcast <8 x i16> %v to <4 x float>
+ ret <4 x float> %res
+}
+
+; CHECK-LABEL: v8i16_to_v2f64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x double> @v8i16_to_v2f64(<8 x i16> %v) {
+ %res = bitcast <8 x i16> %v to <2 x double>
+ ret <2 x double> %res
+}
+
+; CHECK-LABEL: v4i32_to_v16i8:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <16 x i8> @v4i32_to_v16i8(<4 x i32> %v) {
+ %res = bitcast <4 x i32> %v to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v4i32_to_v8i16:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <8 x i16> @v4i32_to_v8i16(<4 x i32> %v) {
+ %res = bitcast <4 x i32> %v to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v4i32_to_v4i32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x i32> @v4i32_to_v4i32(<4 x i32> %v) {
+ %res = bitcast <4 x i32> %v to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v4i32_to_v2i64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x i64> @v4i32_to_v2i64(<4 x i32> %v) {
+ %res = bitcast <4 x i32> %v to <2 x i64>
+ ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v4i32_to_v4f32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x float> @v4i32_to_v4f32(<4 x i32> %v) {
+ %res = bitcast <4 x i32> %v to <4 x float>
+ ret <4 x float> %res
+}
+
+; CHECK-LABEL: v4i32_to_v2f64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x double> @v4i32_to_v2f64(<4 x i32> %v) {
+ %res = bitcast <4 x i32> %v to <2 x double>
+ ret <2 x double> %res
+}
+
+; CHECK-LABEL: v2i64_to_v16i8:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <16 x i8> @v2i64_to_v16i8(<2 x i64> %v) {
+ %res = bitcast <2 x i64> %v to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v2i64_to_v8i16:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <8 x i16> @v2i64_to_v8i16(<2 x i64> %v) {
+ %res = bitcast <2 x i64> %v to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v2i64_to_v4i32:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <4 x i32> @v2i64_to_v4i32(<2 x i64> %v) {
+ %res = bitcast <2 x i64> %v to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v2i64_to_v2i64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <2 x i64> @v2i64_to_v2i64(<2 x i64> %v) {
+ %res = bitcast <2 x i64> %v to <2 x i64>
+ ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v2i64_to_v4f32:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <4 x float> @v2i64_to_v4f32(<2 x i64> %v) {
+ %res = bitcast <2 x i64> %v to <4 x float>
+ ret <4 x float> %res
+}
+
+; CHECK-LABEL: v2i64_to_v2f64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <2 x double> @v2i64_to_v2f64(<2 x i64> %v) {
+ %res = bitcast <2 x i64> %v to <2 x double>
+ ret <2 x double> %res
+}
+
+; CHECK-LABEL: v4f32_to_v16i8:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <16 x i8> @v4f32_to_v16i8(<4 x float> %v) {
+ %res = bitcast <4 x float> %v to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v4f32_to_v8i16:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <8 x i16> @v4f32_to_v8i16(<4 x float> %v) {
+ %res = bitcast <4 x float> %v to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v4f32_to_v4i32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x i32> @v4f32_to_v4i32(<4 x float> %v) {
+ %res = bitcast <4 x float> %v to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v4f32_to_v2i64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x i64> @v4f32_to_v2i64(<4 x float> %v) {
+ %res = bitcast <4 x float> %v to <2 x i64>
+ ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v4f32_to_v4f32:
+; NO-SIMD128-NOT: return $0
+; SIMD128: return $0
+define <4 x float> @v4f32_to_v4f32(<4 x float> %v) {
+ %res = bitcast <4 x float> %v to <4 x float>
+ ret <4 x float> %res
+}
+
+; CHECK-LABEL: v4f32_to_v2f64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM: v128.store
+; SIMD128-VM-NEXT: return{{$}}
+; SIMD128: return $0
+define <2 x double> @v4f32_to_v2f64(<4 x float> %v) {
+ %res = bitcast <4 x float> %v to <2 x double>
+ ret <2 x double> %res
+}
+
+; CHECK-LABEL: v2f64_to_v16i8:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <16 x i8> @v2f64_to_v16i8(<2 x double> %v) {
+ %res = bitcast <2 x double> %v to <16 x i8>
+ ret <16 x i8> %res
+}
+
+; CHECK-LABEL: v2f64_to_v8i16:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <8 x i16> @v2f64_to_v8i16(<2 x double> %v) {
+ %res = bitcast <2 x double> %v to <8 x i16>
+ ret <8 x i16> %res
+}
+
+; CHECK-LABEL: v2f64_to_v4i32:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <4 x i32> @v2f64_to_v4i32(<2 x double> %v) {
+ %res = bitcast <2 x double> %v to <4 x i32>
+ ret <4 x i32> %res
+}
+
+; CHECK-LABEL: v2f64_to_v2i64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <2 x i64> @v2f64_to_v2i64(<2 x double> %v) {
+ %res = bitcast <2 x double> %v to <2 x i64>
+ ret <2 x i64> %res
+}
+
+; CHECK-LABEL: v2f64_to_v4f32:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <4 x float> @v2f64_to_v4f32(<2 x double> %v) {
+ %res = bitcast <2 x double> %v to <4 x float>
+ ret <4 x float> %res
+}
+
+; CHECK-LABEL: v2f64_to_v2f64:
+; NO-SIMD128-NOT: return $0
+; SIMD128-VM-NOT: return $0
+; SIMD128: return $0
+define <2 x double> @v2f64_to_v2f64(<2 x double> %v) {
+ %res = bitcast <2 x double> %v to <2 x double>
+ ret <2 x double> %res
+}
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