[PATCH] D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added a comment.

In https://reviews.llvm.org/D51492#1219494, @avt77 wrote:

> I don't see any changes for VEXTRACTF128 in tests. Do you really need this JWriteVecExtractF128? If YES you should add the corresponding test.


There is no change in tests for VEXTRACTF128 because I didn't touch its latency/throughput profile info.

I need JWriteVecExtractF128 because otherwise I would affect profile info for VEXTRACTF128, which is already correct.
I don't think that I need more tests for it, as there are already existing tests for that instruction (both in llvm-mca and CodeGen/X86).

@lebedev.ri , the amdfam16h SOG also reports that data paths are 128-bits wide. AVX 256-bit instructions are effectively split into two opcodes, and consume twice as many pipeline resources as their 128-bit counterpart. The spreadsheet in the SOG should also report the reciprocal throughput (that's how I derived those resource cycles).


https://reviews.llvm.org/D51492