[PATCH] D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In https://reviews.llvm.org/D51492#1219441, @RKSimon wrote:

> In https://reviews.llvm.org/D51492#1219429, @lebedev.ri wrote:
>
> > Really ignorant question: how do you decide what is the right values?
> >  Is there some documentation?
>
>
> AMD's Fam16h SOG which includes a latency spreadsheet - https://developer.amd.com/resources/developer-guides-manuals/
>
> The Fam15h SOG have similar charts at the back of the PDF as do many of the Intel CPUs in their AOM docs


Hm, perhaps i wrote too much :)
I was specifically asking *not* about the latency/micro-ops, but about the resource cycles.


https://reviews.llvm.org/D51492