[PATCH] D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, avt77, craig.topper, courbet, mattd.
Herald added a subscriber: gbedwell.

This patch fixes the number of micro opcodes, and processor resource cycles for the following AVX instructions:

  vinsertf128rr/rm
  vperm2f128rr/rm

Tests have been regenerated using the usual scripts in the llvm/utils directory.

Please let me know if okay to commit.

Thanks @RKSimon for spotting the issue with WriteFShuffle256.

Andrea


https://reviews.llvm.org/D51492

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/CodeGen/X86/avx-schedule.ll
  test/tools/llvm-mca/X86/BtVer2/resources-avx1.s

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