[PATCH] D51383: [WebAssembly] SIMD loads and stores

[Derek Schuff via Phabricator via llvm-commits]

dschuff added inline comments.


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Comment at: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h:310
+  case WebAssembly::STORE_v2f64:
+  case WebAssembly::STORE_v2f64_S:
   case WebAssembly::ATOMIC_LOAD_I64:
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tlively wrote:
> I'm not actually sure these are in the right place. It looks like this switch returns the log of the default alignment for each type? The spec proposal says, "the memory access size is 16 bytes which is also the natural alignment." Am I reading that correctly to mean that these cases should return 4, not 3?
Yes, that's correct; I'm pretty sure the intention is that the alignment is 16 (4 here). This is a requirement/optimization for some (sub)architectures such as SSE2 (and maybe ARM? not sure), as well as some native C ABIs.


Repository:
  rL LLVM

https://reviews.llvm.org/D51383