[PATCH] D51353: [PowerPC] Optimize compares fed by ANDISo

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai created this revision.
nemanjai added reviewers: inouehrs, hfinkel, kbarton, echristo.

Both ANDIo and ANDISo (and the 64-bit versions) are record-form instructions. When optimizing compares, we handle the former in order to eliminate the compare instruction but not the latter. This patch just adds the latter to the set of instructions we optimize.
The reason these instructions need to be handled separately is that they are not part of the `RecFormRel` map (since they don't have a non-record-form). The missing "and-immediate-shifted" is just an oversight in the initial implementation.


Repository:
  rL LLVM

https://reviews.llvm.org/D51353

Files:
  lib/Target/PowerPC/PPCInstrInfo.cpp
  test/CodeGen/PowerPC/optimize-andiso.ll


Index: test/CodeGen/PowerPC/optimize-andiso.ll
===================================================================
--- test/CodeGen/PowerPC/optimize-andiso.ll
+++ test/CodeGen/PowerPC/optimize-andiso.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s
+define float @floatundisf(i64 %a) {
+; CHECK-LABEL: floatundisf:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    xxlxor f1, f1, f1
+; CHECK-NEXT:    blr
+; CHECK-NEXT:  .LBB0_2: # %sw.epilog
+; CHECK-NEXT:    addi r3, r3, 1
+; CHECK-NEXT:    li r5, 2
+; CHECK-NEXT:    andis. r4, r3, 1024
+; CHECK-NEXT:    li r4, 3
+; CHECK-NEXT:    isel r4, r5, r4, eq
+; CHECK-NEXT:    srd r3, r3, r4
+; CHECK-NEXT:    rlwinm r3, r3, 0, 9, 31
+; CHECK-NEXT:    mtvsrd f0, r3
+; CHECK-NEXT:    xxsldwi vs0, vs0, vs0, 1
+; CHECK-NEXT:    xscvspdpn f1, vs0
+; CHECK-NEXT:    blr
+entry:
+  br i1 undef, label %return, label %sw.epilog
+
+sw.epilog:                                        ; preds = %entry
+  %or14 = or i64 0, %a
+  %inc = add i64 %or14, 1
+  %and16 = and i64 %inc, 67108864
+  %tobool = icmp eq i64 %and16, 0
+  %tmp.select.v = select i1 %tobool, i64 2, i64 3
+  %tmp.select = lshr i64 %inc, %tmp.select.v
+  %conv26 = trunc i64 %tmp.select to i32
+  %and27 = and i32 %conv26, 8388607
+  %or28 = or i32 0, %and27
+  %0 = bitcast i32 %or28 to float
+  br label %return
+
+return:                                           ; preds = %sw.epilog, %entry
+  %retval.0 = phi float [ %0, %sw.epilog ], [ 0.000000e+00, %entry ]
+  ret float %retval.0
+}
Index: lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- lib/Target/PowerPC/PPCInstrInfo.cpp
+++ lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1822,7 +1822,8 @@
 
   int NewOpC = -1;
   int MIOpC = MI->getOpcode();
-  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8)
+  if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 ||
+      MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8)
     NewOpC = MIOpC;
   else {
     NewOpC = PPC::getRecordFormOpcode(MIOpC);


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