[PATCH] D50857: llvm: Add support MIPS r6 Debian triples

Simon Atanasyan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 28 02:38:38 PDT 2018


atanasyan added a comment.

It would be nice to split this patch - the first one introduces new https://reviews.llvm.org/source/compiler-rt/ target triples, the second one fixes N32 ABI handling.



================
Comment at: lib/Support/Triple.cpp:401
     .Case("msp430", Triple::msp430)
-    .Cases("mips", "mipseb", "mipsallegrex", Triple::mips)
-    .Cases("mipsel", "mipsallegrexel", Triple::mipsel)
-    .Cases("mips64", "mips64eb", Triple::mips64)
-    .Case("mips64el", Triple::mips64el)
+    .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6",
+           "mipsr6", Triple::mips)
----------------
Could you add test case for that code? To the TripleTest.cpp for example.


================
Comment at: lib/Support/Triple.cpp:545
 static Triple::SubArchType parseSubArch(StringRef SubArchName) {
+  if (SubArchName.startswith("mipsisa32r6") ||
+      SubArchName.startswith("mipsisa64r6") ||
----------------
Does the `SubArchName.startswith("mips") && (SubArchName.endswith("r6el") || SubArchName.endswith("r6"))` expression cover "mipsisa32r6" and "mipsisa64r6" cases as well?


================
Comment at: lib/Support/Triple.cpp:723
+    } else {
+      Environment = StringSwitch<Triple::EnvironmentType>(Components[0])
+                        .StartsWith("mipsn32", Triple::GNUABIN32)
----------------
Could you add test case for that code? To the TripleTest.cpp for example.


================
Comment at: lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp:58
     return MipsABIInfo::N64();
+  if(TT.getEnvironment() == llvm::Triple::GNUABIN32)
+    return MipsABIInfo::N32();
----------------
clang-format this line


================
Comment at: lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp:578
+    n32 = true;
+  else if (Options.ABIName.empty() && STI.getTargetTriple().getEnvironment() == Triple::GNUABIN32)
+    n32 = true;
----------------
Ditto


Repository:
  rL LLVM

https://reviews.llvm.org/D50857





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