[PATCH] D51203: AMDGPU: Handle 32-bit address wraparounds for SMRD opcodes

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

Right, that matches my understanding: the SMRD/SMEM instruction does a 64-bit addition, so if the 32-bit (add X, imm) were to have an unsigned wraparound, moving it into the immediate of the SMRD/SMEM would remove the wraparound and therefore be incorrect.

Conversely, if the 32-bit add is nuw, then putting the immediate into the SMEM is okay. So we should definitely add this as a condition that allows the move.

The question is: what to do about the 256 KiB condition? It is rather hacky, so ideally we'd do without, but that requires us to figure out how earlier passes can be coaxed into generating adds with nuw set (or live with less efficient code, which would suck). This needs looking at the getelementptr lowering.


Repository:
  rL LLVM

https://reviews.llvm.org/D51203