[PATCH] D46179: [X86] Lowering addus/subus intrinsics to native IR (LLVM part)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D46179#1211902, @srj wrote:

> Disabling all our optimizer passes 'fixes' this but that's obviously unsuitable as a solution. Could this pattern matching be made more robust?


Would it help or hurt if we narrowed the select in IR to match the final return type and original operand types (I made the types smaller from your code just to make this easier to read):

  define <2 x i8> @should_narrow_select(<2 x i8> %x, <2 x i1> %cmp) {
    %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
    %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
    %widesel = select <4 x i1> %widecmp, <4 x i8> <i8 -1, i8 -1, i8 undef, i8 undef>, <4 x i8> %widex
    %sel = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
    ret <2 x i8> %sel
  }

-->

  define <2 x i8> @should_narrow_select(<2 x i8> %x, <2 x i1> %cmp) {
    %narrowsel = select <2 x i1> %cmp, <2 x i8> <i8 -1, i8 -1>, <2 x i8> %x
    ret <2 x i8> %narrowsel
  }


Repository:
  rL LLVM

https://reviews.llvm.org/D46179