[PATCH] D51147: [GISel]: Remove an incorrect assert in CallLowering

[Aditya Nandakumar via Phabricator via llvm-commits]

aditya_nandakumar updated this revision to Diff 162261.
aditya_nandakumar added a comment.

Thanks Daniel. Added test case.


https://reviews.llvm.org/D51147

Files:
  lib/CodeGen/GlobalISel/CallLowering.cpp
  test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll


Index: test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/GlobalISel/calllowering-nocrashret.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -o - -global-isel %s -stop-after=irtranslator | FileCheck %s
+
+define <4 x i1> @foo() {
+  ; CHECK-LABEL: name: foo
+  ; CHECK: bb.1.entry:
+  ; CHECK:   [[DEF:%[0-9]+]]:_(<4 x s1>) = G_IMPLICIT_DEF
+  ; CHECK:   [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[DEF]](<4 x s1>)
+  ; CHECK:   $xmm0 = COPY [[ANYEXT]](<4 x s32>)
+  ; CHECK:   RET 0, implicit $xmm0
+entry:
+  ret <4 x i1> undef ;
+}
Index: lib/CodeGen/GlobalISel/CallLowering.cpp
===================================================================
--- lib/CodeGen/GlobalISel/CallLowering.cpp
+++ lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -164,7 +164,6 @@
     // nop in big-endian situations.
     return ValReg;
   case CCValAssign::AExt: {
-    assert(!VA.getLocVT().isVector() && "unexpected vector extend");
     auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
     return MIB->getOperand(0).getReg();
   }


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