[PATCH] D50914: [RegisterCoalescer] Fix for assert in removePartialRedundancy

[Tim Renouf via Phabricator via llvm-commits]

tpr marked an inline comment as done.
tpr added inline comments.


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Comment at: test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir:11-14
+registers:       
+  - { id: 0, class: sreg_128 }
+  - { id: 1, class: sreg_128 }
+  - { id: 2, class: sreg_128 }
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MatzeB wrote:
> Could you try if the test still works with the `registers:` block removed? It seems the machine operands below have the register classes annotated anyway.
Yes, it does work without the registers: block. I will remove it.


Repository:
  rL LLVM

https://reviews.llvm.org/D50914