[PATCH] D51156: Handle identifying AMDGPU bitcode files

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: ruiu, kzhuravl.
Herald added subscribers: dexonsmith, steven_wu, arichardson, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, emaste.
Herald added a reviewer: espindola.

https://reviews.llvm.org/D51156

Files:
  ELF/InputFiles.cpp
  test/ELF/lto/amdgcn.ll
  test/ELF/lto/r600.ll


Index: test/ELF/lto/r600.ll
===================================================================
--- /dev/null
+++ test/ELF/lto/r600.ll
@@ -0,0 +1,12 @@
+; REQUIRES: amdgpu
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+
+; Make sure the r600 triple is handled
+
+target triple = "r600-mesa-mes3d"
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+
+define void @_start() {
+  ret void
+}
Index: test/ELF/lto/amdgcn.ll
===================================================================
--- /dev/null
+++ test/ELF/lto/amdgcn.ll
@@ -0,0 +1,12 @@
+; REQUIRES: amdgpu
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+
+; Make sure the amdgcn triple is handled
+
+target triple = "amdgcn-amd-amdhsa"
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+
+define void @_start() {
+  ret void
+}
Index: ELF/InputFiles.cpp
===================================================================
--- ELF/InputFiles.cpp
+++ ELF/InputFiles.cpp
@@ -1071,6 +1071,9 @@
     return T.isOSIAMCU() ? EM_IAMCU : EM_386;
   case Triple::x86_64:
     return EM_X86_64;
+  case Triple::amdgcn:
+  case Triple::r600:
+    return EM_AMDGPU;
   default:
     error(Path + ": could not infer e_machine from bitcode target triple " +
           T.str());


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