[PATCH] D51122: [PowerPC][MC] Support expressions in getMemRIX16Encoding

[Sean Fertile via Phabricator via llvm-commits]

sfertile created this revision.
sfertile added reviewers: nemanjai, hfinkel, syzaara.
Herald added a subscriber: kbarton.

Loosens an assert in  getMemRIX16Encoding that restricts DQ-form instructions to using an immediate, so that we can assemble instructions like  `lxv   3,    global at toc@l(3)`


Repository:
  rL LLVM

https://reviews.llvm.org/D51122

Files:
  lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  test/MC/PowerPC/ppc64-dq-expr.s


Index: test/MC/PowerPC/ppc64-dq-expr.s
===================================================================
--- /dev/null
+++ test/MC/PowerPC/ppc64-dq-expr.s
@@ -0,0 +1,38 @@
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu %s -filetype=obj -o - | \
+# RUN:    llvm-objdump -D  -r - | FileCheck %s
+        .text
+        .abiversion 2
+        .global test
+        .p2align 4
+        .type test, at function
+test:
+.Lgep:
+        addis 2, 12, .TOC.-.Lgep at ha
+        addi  2,  2, .TOC.-.Lgep at l
+.Llep:
+        .localentry  test, .Llep-.Lgep
+        addis 3, 2, vecA at toc@ha
+        lxv   3,    vecA at toc@l(3)
+        addis 3, 2, vecB at toc@ha
+        stxv  3,    vecB at toc@l(3)
+        blr
+
+        .comm  vecA, 16, 16
+        .comm  vecB, 16, 16
+
+# CHECK: Disassembly of section .text:
+# CHECK-LABEL: test:
+# CHECK-NEXT:    addis 2, 12, 0
+# CHECK-NEXT:    R_PPC64_REL16_HA     .TOC.
+# CHECK-NEXT:    addi 2, 2, 0
+# CHECK-NEXT:    R_PPC64_REL16_LO     .TOC.
+# CHECK-NEXT:    addis 3, 2, 0
+# CHECK-NEXT:    R_PPC64_TOC16_HA     vecA
+# CHECK-NEXT:    lxv 3, 0(3)
+# CHECK-NEXT:    R_PPC64_TOC16_LO_DS  vecA
+# CHECK-NEXT:    addis 3, 2, 0
+# CHECK-NEXT:    R_PPC64_TOC16_HA     vecB
+# CHECK-NEXT:    stxv 3, 0(3)
+# CHECK-NEXT:    R_PPC64_TOC16_LO_DS  vecB
+# CHECK-NEXT:    blr
+
Index: lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
===================================================================
--- lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -264,10 +264,16 @@
   unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 12;
 
   const MCOperand &MO = MI.getOperand(OpNo);
-  assert(MO.isImm() && !(MO.getImm() % 16) &&
-         "Expecting an immediate that is a multiple of 16");
+  if (MO.isImm()) {
+    assert(!(MO.getImm() % 16) &&
+           "Expecting an immediate that is a multiple of 16");
+    return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
+  }
 
-  return ((getMachineOpValue(MI, MO, Fixups, STI) >> 4) & 0xFFF) | RegBits;
+  // Otherwise add a fixup for the displacement field.
+  Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 2, MO.getExpr(),
+                                   (MCFixupKind)PPC::fixup_ppc_half16ds));
+  return RegBits;
 }
 
 unsigned PPCMCCodeEmitter::getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,


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