[PATCH] D51030: [AArch64] Optimise load(adr address) to ldr address

[John Brawn via Phabricator via llvm-commits]

john.brawn added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:1098
 
+bool AArch64DAGToDAGISel::tryAdrLoad(SDNode *N) {
+  // Look for a load(adr <addr>) where the addr is 4 byte aligned
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I'm pretty sure we can do the selection entirely in tablegen. I experimented with adjusting LoadLiteral AArch64InstrFormats.td to be kinda similar to Load32RO (take ValueType and SDPatternOperator as arguments, use these in a pattern but match AArch64adr for the address) and that seemed to work. The only problem there is making sure the alignment is correct, which I think can be done using a PatFrag or PatLeaf (though I tried something quick and ran into tablegen errors, so maybe it's more complicated than I expect).


https://reviews.llvm.org/D51030