[PATCH] D51094: AMDGPU: Fix not respecting byval alignment in call frame setup

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, scott.linder.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

This was hackily adding in the 4-bytes reserved for the callee's
emergency stack slot. Treat it like a normal stack allocation
so we get the correct alignment padding behavior. This fixes
an inconsistency between the caller and callee.


https://reviews.llvm.org/D51094

Files:
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  lib/Target/AMDGPU/AMDGPUISelLowering.h
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.h
  test/CodeGen/AMDGPU/byval-frame-setup.ll
  test/CodeGen/AMDGPU/callee-special-input-vgprs.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D51094.161915.patch
Type: text/x-patch
Size: 17563 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180822/627c4a6c/attachment.bin>