[llvm] r340158 - [AArch64][SVE] Asm: Add SVE System registers
Hans Wennborg via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 21 15:49:57 PDT 2018
Merged to 7.0 in r340355.
On Mon, Aug 20, 2018 at 2:16 AM, Sander de Smalen via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: s.desmalen
> Date: Mon Aug 20 02:16:59 2018
> New Revision: 340158
>
> URL: http://llvm.org/viewvc/llvm-project?rev=340158&view=rev
> Log:
> [AArch64][SVE] Asm: Add SVE System registers
>
> This patch adds system registers for controlling aspects of SVE:
> - ZCR_EL1 (r/w) visible at EL1 and EL0.
> - ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0.
> - ZCR_EL3 (r/w) visible at all exception levels.
>
> and a system register identifying SVE:
> - ID_AA64ZFR0_EL1 (r) SVE Feature identifier.
>
> Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar
>
> Reviewed By: SjoerdMeijer
>
> Differential Revision: https://reviews.llvm.org/D50885
>
> Added:
> llvm/trunk/test/MC/AArch64/SVE/system-regs-diagnostics.s
> llvm/trunk/test/MC/AArch64/SVE/system-regs.s
> Modified:
> llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=340158&r1=340157&r2=340158&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Mon Aug 20 02:16:59 2018
> @@ -576,6 +576,12 @@ def : ROSysReg<"ICH_VTR_EL2", 0b1
> def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
> def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
>
> +// SVE control registers
> +// Op0 Op1 CRn CRm Op2
> +let Requires = [{ {AArch64::FeatureSVE} }] in {
> +def : ROSysReg<"ID_AA64ZFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b100>;
> +}
> +
> // v8.1a "Limited Ordering Regions" extension-specific system register
> // Op0 Op1 CRn CRm Op2
> let Requires = [{ {AArch64::HasV8_1aOps} }] in
> @@ -1311,6 +1317,15 @@ def : RWSysReg<"VNCR_EL2", 0b11,
>
> } // HasV8_4aOps
>
> +// SVE control registers
> +// Op0 Op1 CRn CRm Op2
> +let Requires = [{ {AArch64::FeatureSVE} }] in {
> +def : RWSysReg<"ZCR_EL1", 0b11, 0b000, 0b0001, 0b0010, 0b000>;
> +def : RWSysReg<"ZCR_EL2", 0b11, 0b100, 0b0001, 0b0010, 0b000>;
> +def : RWSysReg<"ZCR_EL3", 0b11, 0b110, 0b0001, 0b0010, 0b000>;
> +def : RWSysReg<"ZCR_EL12", 0b11, 0b101, 0b0001, 0b0010, 0b000>;
> +}
> +
> // Cyclone specific system registers
> // Op0 Op1 CRn CRm Op2
> let Requires = [{ {AArch64::ProcCyclone} }] in
>
> Added: llvm/trunk/test/MC/AArch64/SVE/system-regs-diagnostics.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/system-regs-diagnostics.s?rev=340158&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/SVE/system-regs-diagnostics.s (added)
> +++ llvm/trunk/test/MC/AArch64/SVE/system-regs-diagnostics.s Mon Aug 20 02:16:59 2018
> @@ -0,0 +1,51 @@
> +// RUN: not llvm-mc -triple aarch64 -mattr=+sve -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SVE
> +// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOSVE
> +
> +
> +// --------------------------------------------------------------------------//
> +// ID_AA64ZFR0_EL1 is read-only
> +
> +msr ID_AA64ZFR0_EL1, x3
> +// CHECK-SVE: error: expected writable system register or pstate
> +// CHECK-SVE-NEXT: msr ID_AA64ZFR0_EL1, x3
> +
> +
> +// --------------------------------------------------------------------------//
> +// Check that the other SVE registers are only readable/writable when
> +// the +sve attribute is set.
> +
> +mrs x3, ID_AA64ZFR0_EL1
> +// CHECK-NOSVE: error: expected readable system register
> +// CHECK-NOSVE: mrs x3, ID_AA64ZFR0_EL1
> +
> +mrs x3, ZCR_EL1
> +// CHECK-NOSVE: error: expected readable system register
> +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL1
> +
> +mrs x3, ZCR_EL2
> +// CHECK-NOSVE: error: expected readable system register
> +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL2
> +
> +mrs x3, ZCR_EL3
> +// CHECK-NOSVE: error: expected readable system register
> +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL3
> +
> +mrs x3, ZCR_EL12
> +// CHECK-NOSVE: error: expected readable system register
> +// CHECK-NOSVE-NEXT: mrs x3, ZCR_EL12
> +
> +msr ZCR_EL1, x3
> +// CHECK-NOSVE: error: expected writable system register or pstate
> +// CHECK-NOSVE-NEXT: msr ZCR_EL1, x3
> +
> +msr ZCR_EL2, x3
> +// CHECK-NOSVE: error: expected writable system register or pstate
> +// CHECK-NOSVE-NEXT: msr ZCR_EL2, x3
> +
> +msr ZCR_EL3, x3
> +// CHECK-NOSVE: error: expected writable system register or pstate
> +// CHECK-NOSVE-NEXT: msr ZCR_EL3, x3
> +
> +msr ZCR_EL12, x3
> +// CHECK-NOSVE: error: expected writable system register or pstate
> +// CHECK-NOSVE-NEXT: msr ZCR_EL12, x3
>
> Added: llvm/trunk/test/MC/AArch64/SVE/system-regs.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/system-regs.s?rev=340158&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/SVE/system-regs.s (added)
> +++ llvm/trunk/test/MC/AArch64/SVE/system-regs.s Mon Aug 20 02:16:59 2018
> @@ -0,0 +1,62 @@
> +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
> +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
> +// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
> +// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
> +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
> +// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
> +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
> +// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
> +
> +mrs x3, ID_AA64ZFR0_EL1
> +// CHECK-INST: mrs x3, ID_AA64ZFR0_EL1
> +// CHECK-ENCODING: [0x83,0x04,0x38,0xd5]
> +// CHECK-ERROR: expected readable system register
> +// CHECK-UNKNOWN: 83 04 38 d5 mrs x3, S3_0_C0_C4_4
> +
> +mrs x3, ZCR_EL1
> +// CHECK-INST: mrs x3, ZCR_EL1
> +// CHECK-ENCODING: [0x03,0x12,0x38,0xd5]
> +// CHECK-ERROR: expected readable system register
> +// CHECK-UNKNOWN: 03 12 38 d5 mrs x3, S3_0_C1_C2_0
> +
> +mrs x3, ZCR_EL2
> +// CHECK-INST: mrs x3, ZCR_EL2
> +// CHECK-ENCODING: [0x03,0x12,0x3c,0xd5]
> +// CHECK-ERROR: expected readable system register
> +// CHECK-UNKNOWN: 03 12 3c d5 mrs x3, S3_4_C1_C2_0
> +
> +mrs x3, ZCR_EL3
> +// CHECK-INST: mrs x3, ZCR_EL3
> +// CHECK-ENCODING: [0x03,0x12,0x3e,0xd5]
> +// CHECK-ERROR: expected readable system register
> +// CHECK-UNKNOWN: 03 12 3e d5 mrs x3, S3_6_C1_C2_0
> +
> +mrs x3, ZCR_EL12
> +// CHECK-INST: mrs x3, ZCR_EL12
> +// CHECK-ENCODING: [0x03,0x12,0x3d,0xd5]
> +// CHECK-ERROR: expected readable system register
> +// CHECK-UNKNOWN: 03 12 3d d5 mrs x3, S3_5_C1_C2_0
> +
> +msr ZCR_EL1, x3
> +// CHECK-INST: msr ZCR_EL1, x3
> +// CHECK-ENCODING: [0x03,0x12,0x18,0xd5]
> +// CHECK-ERROR: expected writable system register or pstate
> +// CHECK-UNKNOWN: 03 12 18 d5 msr S3_0_C1_C2_0, x3
> +
> +msr ZCR_EL2, x3
> +// CHECK-INST: msr ZCR_EL2, x3
> +// CHECK-ENCODING: [0x03,0x12,0x1c,0xd5]
> +// CHECK-ERROR: expected writable system register or pstate
> +// CHECK-UNKNOWN: 03 12 1c d5 msr S3_4_C1_C2_0, x3
> +
> +msr ZCR_EL3, x3
> +// CHECK-INST: msr ZCR_EL3, x3
> +// CHECK-ENCODING: [0x03,0x12,0x1e,0xd5]
> +// CHECK-ERROR: expected writable system register or pstate
> +// CHECK-UNKNOWN: 03 12 1e d5 msr S3_6_C1_C2_0, x3
> +
> +msr ZCR_EL12, x3
> +// CHECK-INST: msr ZCR_EL12, x3
> +// CHECK-ENCODING: [0x03,0x12,0x1d,0xd5]
> +// CHECK-ERROR: expected writable system register or pstate
> +// CHECK-UNKNOWN: 03 12 1d d5 msr S3_5_C1_C2_0, x3
>
>
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