[PATCH] D50982: [AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions

[Scott Linder via Phabricator via llvm-commits]

scott.linder updated this revision to Diff 161793.
scott.linder added a comment.

Use variables for registers in MIR tests. Add IR tests, trying to cover problem cases around introducing control flow. There is another case in the indirect-addressing tests with an SGPR def between the two operations, but I'm not sure what it is testing. Are the tests I added useful, and are there still more you can think of to add?

I will start working on a patch with a generic waterfall emitter, and I will talk to the graphics devs about how to fix the `readfirstlane` shortcut and the addrspace hack.


https://reviews.llvm.org/D50982

Files:
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  test/CodeGen/AMDGPU/mubuf-legalize-operands.mir

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