[PATCH] D48580: [AArch64] Support reserving x1-7 registers.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> IIUC, miscompilation can happen if caller and callee have different sets of reserved registers.

This is not the problem, at all.  The problem is simply ensuring that the option does something sane.  gcc effectively ignores the option in some cases.  For example, consider the following with -ffixed-x1:

  struct S { int x[100]; };
  struct S x, y;
  void f() { x=y; }

gcc generates the instruction "add     x1, x3, :lo12:y", which violates the request to reserve x1.  With the current version of the patch, LLVM will do something similar.

So we have the following options:

- Copy gcc's behavior, ignore that it's broken, and wait for someone to file a bug when a new version of clang breaks the Linux kernel.
- Come up with some way to reliably avoid situations like the testcase.  Maybe some combination of error messages in situations where the compiler would generate broken code, generating inline implementations instead of libcalls, and avoiding certain optimizations.  This is complicated, and I'm not sure it's really worth the effort when exactly one file in the whole world would use the option.
- Don't support -ffixed-x1, and convince the kernel maintainers not to require it.


Repository:
  rL LLVM

https://reviews.llvm.org/D48580