[PATCH] D50992: [InstCombine] try to fold insertelt + vector op into scalar op + insertelt

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'm concerned the backend won't reliably reverse the transform. For integer operations, SelectionDAG heavily depends on IR types to decide whether to perform an operation in integer or SIMD registers, and transferring values between the two register files is slow.  Yes, the second of an insertelement is a scalar, but many backends pattern-match a load+insertelement to a vector register load.

I agree this makes sense for IR.


https://reviews.llvm.org/D50992