[llvm] r339977 - [GISel]: Add Opcodes for a few LLVM Intrinsics

Mon Aug 20 13:19:39 PDT 2018

NP, and sorry couldn't get it fixed in place. Let me know if you need any
help.

On Mon, Aug 20, 2018 at 11:07 AM Aditya Nandakumar <
aditya_nandakumar at apple.com> wrote:

> Hi Chandler,
>
> I completely missed this email. Thanks for reverting. I’ll look into this
> now (and another related commit).
>
> Aditya
>
>
> On Aug 16, 2018, at 9:33 PM, Chandler Carruth <chandlerc at gmail.com> wrote:
>
> As it has been well over 2 hours without update, i'm going to just revert.
>
> On Thu, Aug 16, 2018 at 7:42 PM Chandler Carruth <chandlerc at gmail.com>
> wrote:
>
>> (and lots of other bots it looks like)
>>
>> On Thu, Aug 16, 2018 at 7:39 PM Chandler Carruth <chandlerc at gmail.com>
>> wrote:
>>
>>> Not sure the bot blame will work, but pretty sure this broke LTO bots:
>>>
>>> http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/12107/steps/test-stage2-compiler/logs/stdio
>>>
>>> http://lab.llvm.org:8011/builders/clang-with-lto-ubuntu/builds/9867/steps/test-stage2-compiler/logs/stdio
>>>
>>> On Thu, Aug 16, 2018 at 6:42 PM Aditya Nandakumar via llvm-commits <
>>> llvm-commits at lists.llvm.org> wrote:
>>>
>>>> Author: aditya_nandakumar
>>>> Date: Thu Aug 16 18:41:56 2018
>>>> New Revision: 339977
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=339977&view=rev
>>>> Log:
>>>> [GISel]: Add Opcodes for a few LLVM Intrinsics
>>>>
>>>> https://reviews.llvm.org/D50401
>>>>
>>>> Add opcodes for llvm.intrinsic.trunc, round, and update the IRTranslator
>>>> for the same.
>>>>
>>>> Reviewed by: dsanders.
>>>>
>>>> Modified:
>>>>     llvm/trunk/include/llvm/Support/TargetOpcodes.def
>>>>     llvm/trunk/include/llvm/Target/GenericOpcodes.td
>>>>     llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
>>>>     llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
>>>>
>>>> Modified: llvm/trunk/include/llvm/Support/TargetOpcodes.def
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetOpcodes.def?rev=339977&r1=339976&r2=339977&view=diff
>>>>
>>>> ==============================================================================
>>>> --- llvm/trunk/include/llvm/Support/TargetOpcodes.def (original)
>>>> +++ llvm/trunk/include/llvm/Support/TargetOpcodes.def Thu Aug 16
>>>> 18:41:56 2018
>>>> @@ -268,6 +268,12 @@ HANDLE_TARGET_OPCODE(G_INTTOPTR)
>>>>  /// COPY is the relevant instruction.
>>>>  HANDLE_TARGET_OPCODE(G_BITCAST)
>>>>
>>>> +/// INTRINSIC trunc intrinsic.
>>>> +HANDLE_TARGET_OPCODE(G_INTRINSIC_TRUNC)
>>>> +
>>>> +/// INTRINSIC round intrinsic.
>>>> +HANDLE_TARGET_OPCODE(G_INTRINSIC_ROUND)
>>>> +
>>>>  /// Generic load (including anyext load)
>>>>  HANDLE_TARGET_OPCODE(G_LOAD)
>>>>
>>>>
>>>> Modified: llvm/trunk/include/llvm/Target/GenericOpcodes.td
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GenericOpcodes.td?rev=339977&r1=339976&r2=339977&view=diff
>>>>
>>>> ==============================================================================
>>>> --- llvm/trunk/include/llvm/Target/GenericOpcodes.td (original)
>>>> +++ llvm/trunk/include/llvm/Target/GenericOpcodes.td Thu Aug 16
>>>> 18:41:56 2018
>>>> @@ -513,6 +513,21 @@ def G_FLOG2 : GenericInstruction {
>>>>  }
>>>>
>>>>
>>>>  //------------------------------------------------------------------------------
>>>> +// Opcodes for LLVM Intrinsics
>>>>
>>>> +//------------------------------------------------------------------------------
>>>> +def G_INTRINSIC_TRUNC : GenericInstruction {
>>>> +  let OutOperandList = (outs type0:$dst);
>>>> +  let InOperandList = (ins type0:$src1);
>>>> +  let hasSideEffects = 0;
>>>> +}
>>>> +
>>>> +def G_INTRINSIC_ROUND : GenericInstruction {
>>>> +  let OutOperandList = (outs type0:$dst);
>>>> +  let InOperandList = (ins type0:$src1);
>>>> +  let hasSideEffects = 0;
>>>> +}
>>>> +
>>>>
>>>> +//------------------------------------------------------------------------------
>>>>  // Memory ops
>>>>
>>>>  //------------------------------------------------------------------------------
>>>>
>>>>
>>>> Modified: llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp?rev=339977&r1=339976&r2=339977&view=diff
>>>>
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp (original)
>>>> +++ llvm/trunk/lib/CodeGen/GlobalISel/IRTranslator.cpp Thu Aug 16
>>>> 18:41:56 2018
>>>> @@ -850,6 +850,16 @@ bool IRTranslator::translateKnownIntrins
>>>>          .addDef(getOrCreateVReg(CI))
>>>>          .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
>>>>      return true;
>>>> +  case Intrinsic::trunc:
>>>> +    MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC)
>>>> +        .addDef(getOrCreateVReg(CI))
>>>> +        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
>>>> +    return true;
>>>> +  case Intrinsic::round:
>>>> +    MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_ROUND)
>>>> +        .addDef(getOrCreateVReg(CI))
>>>> +        .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
>>>> +    return true;
>>>>    case Intrinsic::fma:
>>>>      MIRBuilder.buildInstr(TargetOpcode::G_FMA)
>>>>          .addDef(getOrCreateVReg(CI))
>>>>
>>>> Modified:
>>>> llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll?rev=339977&r1=339976&r2=339977&view=diff
>>>>
>>>> ==============================================================================
>>>> --- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
>>>> (original)
>>>> +++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
>>>> Thu Aug 16 18:41:56 2018
>>>> @@ -1408,6 +1408,26 @@ define float @test_fabs_intrin(float %a)
>>>>    ret float %res
>>>>  }
>>>>
>>>> +declare float @llvm.trunc.f32(float)
>>>> +define float @test_intrinsic_trunc(float %a) {
>>>> +; CHECK-LABEL: name: test_intrinsic_trunc
>>>> +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
>>>> +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[A]]
>>>> +; CHECK: $s0 = COPY [[RES]]
>>>> +  %res = call float @llvm.trunc.f32(float %a)
>>>> +  ret float %res
>>>> +}
>>>> +
>>>> +declare float @llvm.round.f32(float)
>>>> +define float @test_intrinsic_round(float %a) {
>>>> +; CHECK-LABEL: name: test_intrinsic_round
>>>> +; CHECK: [[A:%[0-9]+]]:_(s32) = COPY $s0
>>>> +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[A]]
>>>> +; CHECK: $s0 = COPY [[RES]]
>>>> +  %res = call float @llvm.round.f32(float %a)
>>>> +  ret float %res
>>>> +}
>>>> +
>>>>  declare i32 @llvm.ctlz.i32(i32, i1)
>>>>  define i32 @test_ctlz_intrinsic_zero_not_undef(i32 %a) {
>>>>  ; CHECK-LABEL: name: test_ctlz_intrinsic_zero_not_undef
>>>>
>>>>
>>>> _______________________________________________
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>>>>
>>>
>
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