[PATCH] D50437: [mips] Implement pll.ps, plu.ps and some of the missing cvt.* instructions

[Aleksandar Beserminji via Phabricator via llvm-commits]

abeserminji planned changes to this revision.
abeserminji added a comment.

After reviewing the instruction manual again, I noticed the following in the Restrictions section:
//The result of this instruction is UNPREDICTABLE if the processor is executing in the FR=0 32-bit FPU register model; it is predictable if executing on a 64-bit FPU in the FR=1 mode, but not with FR=0, and not on a 32-bit FPU.//
Which makes some of the definitions in the patch wrong. Should fix that.


https://reviews.llvm.org/D50437