[llvm] r340123 - [X86] Merge shift/rotate schedule class instregexs
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 18 08:58:19 PDT 2018
Author: rksimon
Date: Sat Aug 18 08:58:19 2018
New Revision: 340123
URL: http://llvm.org/viewvc/llvm-project?rev=340123&view=rev
Log:
[X86] Merge shift/rotate schedule class instregexs
Helps reduce cost of instrw collection
Modified:
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=340123&r1=340122&r2=340123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sat Aug 18 08:58:19 2018
@@ -654,10 +654,8 @@ def BWWriteResGroup13 : SchedWriteRes<[B
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
- "ROL(8|16|32|64)ri",
- "ROR(8|16|32|64)r1",
- "ROR(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r(1|i)",
+ "ROR(8|16|32|64)r(1|i)")>;
def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
let Latency = 2;
@@ -781,10 +779,8 @@ def BWWriteResGroup35 : SchedWriteRes<[B
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
- "RCL(8|16|32|64)ri",
- "RCR(8|16|32|64)r1",
- "RCR(8|16|32|64)ri")>;
+def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
+ "RCR(8|16|32|64)r(1|i)")>;
def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
let Latency = 3;
@@ -1056,12 +1052,9 @@ def BWWriteResGroup69 : SchedWriteRes<[B
def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
"BTR(16|32|64)mi8",
"BTS(16|32|64)mi8",
- "SAR(8|16|32|64)m1",
- "SAR(8|16|32|64)mi",
- "SHL(8|16|32|64)m1",
- "SHL(8|16|32|64)mi",
- "SHR(8|16|32|64)m1",
- "SHR(8|16|32|64)mi")>;
+ "SAR(8|16|32|64)m(1|i)",
+ "SHL(8|16|32|64)m(1|i)",
+ "SHR(8|16|32|64)m(1|i)")>;
def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 6;
@@ -1136,10 +1129,8 @@ def BWWriteResGroup87 : SchedWriteRes<[B
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
- "ROL(8|16|32|64)mi",
- "ROR(8|16|32|64)m1",
- "ROR(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
+ "ROR(8|16|32|64)m(1|i)")>;
def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
let Latency = 7;
@@ -1205,10 +1196,8 @@ def BWWriteResGroup97 : SchedWriteRes<[B
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
- "RCL(8|16|32|64)mi",
- "RCR(8|16|32|64)m1",
- "RCR(8|16|32|64)mi")>;
+def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
+ "RCR(8|16|32|64)m(1|i)")>;
def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
let Latency = 8;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=340123&r1=340122&r2=340123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sat Aug 18 08:58:19 2018
@@ -1092,12 +1092,9 @@ def HWWriteResGroup25 : SchedWriteRes<[H
def: InstRW<[HWWriteResGroup25], (instregex "BTC(16|32|64)mi8",
"BTR(16|32|64)mi8",
"BTS(16|32|64)mi8",
- "SAR(8|16|32|64)m1",
- "SAR(8|16|32|64)mi",
- "SHL(8|16|32|64)m1",
- "SHL(8|16|32|64)mi",
- "SHR(8|16|32|64)m1",
- "SHR(8|16|32|64)mi")>;
+ "SAR(8|16|32|64)m(1|i)",
+ "SHL(8|16|32|64)m(1|i)",
+ "SHR(8|16|32|64)m(1|i)")>;
def HWWriteResGroup26 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 7;
@@ -1119,10 +1116,8 @@ def HWWriteResGroup29 : SchedWriteRes<[H
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r1",
- "ROL(8|16|32|64)ri",
- "ROR(8|16|32|64)r1",
- "ROR(8|16|32|64)ri")>;
+def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r(1|i)",
+ "ROR(8|16|32|64)r(1|i)")>;
def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
let Latency = 2;
@@ -1215,10 +1210,8 @@ def HWWriteResGroup46 : SchedWriteRes<[H
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m1",
- "ROL(8|16|32|64)mi",
- "ROR(8|16|32|64)m1",
- "ROR(8|16|32|64)mi")>;
+def: InstRW<[HWWriteResGroup46], (instregex "ROL(8|16|32|64)m(1|i)",
+ "ROR(8|16|32|64)m(1|i)")>;
def HWWriteResGroup47 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort0156]> {
let Latency = 8;
@@ -1309,10 +1302,8 @@ def HWWriteResGroup59 : SchedWriteRes<[H
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r1",
- "RCL(8|16|32|64)ri",
- "RCR(8|16|32|64)r1",
- "RCR(8|16|32|64)ri")>;
+def: InstRW<[HWWriteResGroup59], (instregex "RCL(8|16|32|64)r(1|i)",
+ "RCR(8|16|32|64)r(1|i)")>;
def HWWriteResGroup60 : SchedWriteRes<[HWPort06,HWPort0156]> {
let Latency = 3;
@@ -1345,10 +1336,8 @@ def HWWriteResGroup66 : SchedWriteRes<[H
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m1",
- "RCL(8|16|32|64)mi",
- "RCR(8|16|32|64)m1",
- "RCR(8|16|32|64)mi")>;
+def: InstRW<[HWWriteResGroup66], (instregex "RCL(8|16|32|64)m(1|i)",
+ "RCR(8|16|32|64)m(1|i)")>;
def HWWriteResGroup67 : SchedWriteRes<[HWPort23,HWPort237,HWPort06,HWPort0156]> {
let Latency = 9;
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=340123&r1=340122&r2=340123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sat Aug 18 08:58:19 2018
@@ -588,10 +588,8 @@ def SBWriteResGroup9 : SchedWriteRes<[SB
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r1",
- "ROL(8|16|32|64)ri",
- "ROR(8|16|32|64)r1",
- "ROR(8|16|32|64)ri",
+def: InstRW<[SBWriteResGroup9], (instregex "ROL(8|16|32|64)r(1|i)",
+ "ROR(8|16|32|64)r(1|i)",
"SET(A|BE)r")>;
def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
@@ -939,12 +937,9 @@ def SBWriteResGroup69 : SchedWriteRes<[S
def: InstRW<[SBWriteResGroup69], (instregex "BTC(16|32|64)mi8",
"BTR(16|32|64)mi8",
"BTS(16|32|64)mi8",
- "SAR(8|16|32|64)m1",
- "SAR(8|16|32|64)mi",
- "SHL(8|16|32|64)m1",
- "SHL(8|16|32|64)mi",
- "SHR(8|16|32|64)m1",
- "SHR(8|16|32|64)mi")>;
+ "SAR(8|16|32|64)m(1|i)",
+ "SHL(8|16|32|64)m(1|i)",
+ "SHR(8|16|32|64)m(1|i)")>;
def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 8;
@@ -982,10 +977,8 @@ def SBWriteResGroup85 : SchedWriteRes<[S
let NumMicroOps = 5;
let ResourceCycles = [1,2,2];
}
-def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m1",
- "ROL(8|16|32|64)mi",
- "ROR(8|16|32|64)m1",
- "ROR(8|16|32|64)mi")>;
+def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
+ "ROR(8|16|32|64)m(1|i)")>;
def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 8;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=340123&r1=340122&r2=340123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sat Aug 18 08:58:19 2018
@@ -669,10 +669,8 @@ def SKLWriteResGroup15 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
- "ROL(8|16|32|64)ri",
- "ROR(8|16|32|64)r1",
- "ROR(8|16|32|64)ri",
+def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r(1|i)",
+ "ROR(8|16|32|64)r(1|i)",
"SET(A|BE)r")>;
def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
@@ -820,10 +818,8 @@ def SKLWriteResGroup42 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",
- "RCL(8|16|32|64)ri",
- "RCR(8|16|32|64)r1",
- "RCR(8|16|32|64)ri")>;
+def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)",
+ "RCR(8|16|32|64)r(1|i)")>;
def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
let Latency = 3;
@@ -1097,12 +1093,9 @@ def SKLWriteResGroup82 : SchedWriteRes<[
def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",
"BTR(16|32|64)mi8",
"BTS(16|32|64)mi8",
- "SAR(8|16|32|64)m1",
- "SAR(8|16|32|64)mi",
- "SHL(8|16|32|64)m1",
- "SHL(8|16|32|64)mi",
- "SHR(8|16|32|64)m1",
- "SHR(8|16|32|64)mi")>;
+ "SAR(8|16|32|64)m(1|i)",
+ "SHL(8|16|32|64)m(1|i)",
+ "SHR(8|16|32|64)m(1|i)")>;
def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 6;
@@ -1217,10 +1210,8 @@ def SKLWriteResGroup100 : SchedWriteRes<
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",
- "ROL(8|16|32|64)mi",
- "ROR(8|16|32|64)m1",
- "ROR(8|16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
+ "ROR(8|16|32|64)m(1|i)")>;
def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
let Latency = 7;
@@ -1306,10 +1297,8 @@ def SKLWriteResGroup116 : SchedWriteRes<
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",
- "RCL(8|16|32|64)mi",
- "RCR(8|16|32|64)m1",
- "RCR(8|16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
+ "RCR(8|16|32|64)m(1|i)")>;
def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
let Latency = 8;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=340123&r1=340122&r2=340123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sat Aug 18 08:58:19 2018
@@ -693,10 +693,8 @@ def SKXWriteResGroup15 : SchedWriteRes<[
let NumMicroOps = 2;
let ResourceCycles = [2];
}
-def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
- "ROL(8|16|32|64)ri",
- "ROR(8|16|32|64)r1",
- "ROR(8|16|32|64)ri",
+def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r(1|i)",
+ "ROR(8|16|32|64)r(1|i)",
"SET(A|BE)r")>;
def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
@@ -887,10 +885,8 @@ def SKXWriteResGroup44 : SchedWriteRes<[
let NumMicroOps = 3;
let ResourceCycles = [1,2];
}
-def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r1",
- "RCL(8|16|32|64)ri",
- "RCR(8|16|32|64)r1",
- "RCR(8|16|32|64)ri")>;
+def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)",
+ "RCR(8|16|32|64)r(1|i)")>;
def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
let Latency = 3;
@@ -1271,12 +1267,9 @@ def SKXWriteResGroup86 : SchedWriteRes<[
def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8",
"BTR(16|32|64)mi8",
"BTS(16|32|64)mi8",
- "SAR(8|16|32|64)m1",
- "SAR(8|16|32|64)mi",
- "SHL(8|16|32|64)m1",
- "SHL(8|16|32|64)mi",
- "SHR(8|16|32|64)m1",
- "SHR(8|16|32|64)mi")>;
+ "SAR(8|16|32|64)m(1|i)",
+ "SHL(8|16|32|64)m(1|i)",
+ "SHR(8|16|32|64)m(1|i)")>;
def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 6;
@@ -1487,10 +1480,8 @@ def SKXWriteResGroup107 : SchedWriteRes<
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m1",
- "ROL(8|16|32|64)mi",
- "ROR(8|16|32|64)m1",
- "ROR(8|16|32|64)mi")>;
+def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)",
+ "ROR(8|16|32|64)m(1|i)")>;
def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
let Latency = 7;
@@ -1665,10 +1656,8 @@ def SKXWriteResGroup127 : SchedWriteRes<
let NumMicroOps = 5;
let ResourceCycles = [1,1,1,2];
}
-def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m1",
- "RCL(8|16|32|64)mi",
- "RCR(8|16|32|64)m1",
- "RCR(8|16|32|64)mi")>;
+def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)",
+ "RCR(8|16|32|64)m(1|i)")>;
def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
let Latency = 8;
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