[PATCH] D50856: [TableGen] Add Logical operands info emission

[Artyom Goncharov via Phabricator via llvm-commits]

m4yers created this revision.
Herald added subscribers: llvm-commits, atanasyan, jrtc27, kbarton, nhaehnle, nemanjai, sdardis, arsenm, MatzeB.
Herald added a reviewer: javed.absar.

This patch is part of a bigger one https://reviews.llvm.org/D50314. It adds a possibility to emit a
logical operands info.

This feature can be used to simplify CISC machine code emission as it done in
M68K https://reviews.llvm.org/D50314 patch. You can check out M680x0MCCodeEmitter.cpp to see how it is
used. In short, it gives a "logical view" onto machine instruction operands
list, as it was defined in the tablegen files.

The main changes are in MCInstrDesc.h and InstrInfoEmitter.cpp, the rest of the
diff is just renaming for consistency sake.


Repository:
  rL LLVM

https://reviews.llvm.org/D50856

Files:
  include/llvm/MC/MCInstrDesc.h
  lib/CodeGen/GlobalISel/LegalizerInfo.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/CodeGen/SelectionDAG/InstrEmitter.cpp
  lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
  lib/CodeGen/TargetInstrInfo.cpp
  lib/CodeGen/TargetSchedule.cpp
  lib/MC/MCInstrAnalysis.cpp
  lib/MC/MCInstrDesc.cpp
  lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
  lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  lib/Target/AMDGPU/GCNHazardRecognizer.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  lib/Target/AMDGPU/SIFoldOperands.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  lib/Target/ARM/ARMBaseInstrInfo.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  lib/Target/ARM/Thumb2SizeReduction.cpp
  lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
  lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
  lib/Target/Lanai/LanaiInstrInfo.cpp
  lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp
  lib/Target/Mips/AsmParser/MipsAsmParser.cpp
  lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
  lib/Target/Mips/MipsSEInstrInfo.cpp
  lib/Target/PowerPC/PPCInstrInfo.cpp
  utils/TableGen/InstrInfoEmitter.cpp

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