[llvm] r339535 - [SelectionDAG] In PromoteIntRes_BITCAST, when the input is TypePromoteFloat, make sure the output type is scalar. For vectors, use a store and load of temporary.

[Hans Wennborg via llvm-commits]

Merged to 7.0 in r339856.

On Mon, Aug 13, 2018 at 8:53 AM, Craig Topper via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
> Author: ctopper
> Date: Sun Aug 12 23:53:47 2018
> New Revision: 339535
>
> URL: http://llvm.org/viewvc/llvm-project?rev=339535&view=rev
> Log:
> [SelectionDAG] In PromoteIntRes_BITCAST, when the input is TypePromoteFloat, make sure the output type is scalar. For vectors, use a store and load of temporary.
>
> Previously if the result type was a vector, we emitted a FP_TO_FP16 with a vector result type which isn't valid.
>
> This is basically the opposite case of the root cause of PR38533.
>
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
>     llvm/trunk/test/CodeGen/X86/pr38533.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=339535&r1=339534&r2=339535&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Sun Aug 12 23:53:47 2018
> @@ -269,8 +269,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
>      return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
>    case TargetLowering::TypePromoteFloat: {
>      // Convert the promoted float by hand.
> -    SDValue PromotedOp = GetPromotedFloat(InOp);
> -    return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
> +    if (!NOutVT.isVector())
> +      return DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, GetPromotedFloat(InOp));
>      break;
>    }
>    case TargetLowering::TypeExpandInteger:
>
> Modified: llvm/trunk/test/CodeGen/X86/pr38533.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=339535&r1=339534&r2=339535&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/pr38533.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/pr38533.ll Sun Aug 12 23:53:47 2018
> @@ -1,6 +1,7 @@
>  ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
>  ; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
>
> +; This test makes sure that a vector that needs to be promoted that is bitcasted to fp16 is legalized correctly without causing a width mismatch.
>  define void @constant_fold_vector_to_half() {
>  ; CHECK-LABEL: constant_fold_vector_to_half:
>  ; CHECK:       # %bb.0:
> @@ -9,3 +10,21 @@ define void @constant_fold_vector_to_hal
>    store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef
>    ret void
>  }
> +
> +; Similarly this makes sure that the opposite bitcast of the above is also legalized without crashing.
> +define void @pr38533_2(half %x) {
> +; CHECK-LABEL: pr38533_2:
> +; CHECK:       # %bb.0:
> +; CHECK-NEXT:    pushq %rax
> +; CHECK-NEXT:    .cfi_def_cfa_offset 16
> +; CHECK-NEXT:    callq __gnu_f2h_ieee
> +; CHECK-NEXT:    movw %ax, {{[0-9]+}}(%rsp)
> +; CHECK-NEXT:    movzwl {{[0-9]+}}(%rsp), %eax
> +; CHECK-NEXT:    movw %ax, (%rax)
> +; CHECK-NEXT:    popq %rax
> +; CHECK-NEXT:    .cfi_def_cfa_offset 8
> +; CHECK-NEXT:    retq
> +  %a = bitcast half %x to <4 x i4>
> +  store volatile <4 x i4> %a, <4 x i4>* undef
> +  ret void
> +}
>
>
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