[llvm] r339823 - [llvm-mca] Minor style changes. NFC
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 15 15:11:05 PDT 2018
Author: adibiagio
Date: Wed Aug 15 15:11:05 2018
New Revision: 339823
URL: http://llvm.org/viewvc/llvm-project?rev=339823&view=rev
Log:
[llvm-mca] Minor style changes. NFC
Modified:
llvm/trunk/tools/llvm-mca/DispatchStage.h
llvm/trunk/tools/llvm-mca/ExecuteStage.h
llvm/trunk/tools/llvm-mca/FetchStage.h
llvm/trunk/tools/llvm-mca/RetireStage.h
Modified: llvm/trunk/tools/llvm-mca/DispatchStage.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/DispatchStage.h?rev=339823&r1=339822&r2=339823&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/DispatchStage.h (original)
+++ llvm/trunk/tools/llvm-mca/DispatchStage.h Wed Aug 15 15:11:05 2018
@@ -49,7 +49,7 @@ class Scheduler;
//
// If the number of micro opcodes exceedes DispatchWidth, then the instruction
// is dispatched in multiple cycles.
-class DispatchStage : public Stage {
+class DispatchStage final : public Stage {
unsigned DispatchWidth;
unsigned AvailableEntries;
unsigned CarryOver;
@@ -92,9 +92,9 @@ public:
// We can always try to dispatch, so returning false is okay in this case.
// The retire stage, which controls the RCU, might have items to complete but
// RetireStage::hasWorkToComplete will check for that case.
- virtual bool hasWorkToComplete() const override final { return false; }
- virtual void cycleStart() override final;
- virtual Status execute(InstRef &IR) override final;
+ bool hasWorkToComplete() const override { return false; }
+ void cycleStart() override;
+ Status execute(InstRef &IR) override;
void notifyDispatchStall(const InstRef &IR, unsigned EventType);
#ifndef NDEBUG
Modified: llvm/trunk/tools/llvm-mca/ExecuteStage.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/ExecuteStage.h?rev=339823&r1=339822&r2=339823&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/ExecuteStage.h (original)
+++ llvm/trunk/tools/llvm-mca/ExecuteStage.h Wed Aug 15 15:11:05 2018
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
/// \file
///
-/// This file defines the execution stage of an instruction pipeline.
+/// This file defines the execution stage of a default instruction pipeline.
///
/// The ExecuteStage is responsible for managing the hardware scheduler
/// and issuing notifications that an instruction has been executed.
@@ -26,7 +26,7 @@
namespace mca {
-class ExecuteStage : public Stage {
+class ExecuteStage final : public Stage {
// Owner will go away when we move listeners/eventing to the stages.
RetireControlUnit &RCU;
Scheduler &HWS;
@@ -36,17 +36,18 @@ class ExecuteStage : public Stage {
void updateSchedulerQueues();
void issueReadyInstructions();
-public:
- ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {}
ExecuteStage(const ExecuteStage &Other) = delete;
ExecuteStage &operator=(const ExecuteStage &Other) = delete;
+public:
+ ExecuteStage(RetireControlUnit &R, Scheduler &S) : Stage(), RCU(R), HWS(S) {}
+
// The ExecuteStage will always complete all of its work per call to
// execute(), so it is never left in a 'to-be-processed' state.
- virtual bool hasWorkToComplete() const override final { return false; }
+ bool hasWorkToComplete() const override { return false; }
- virtual void cycleStart() override final;
- virtual Status execute(InstRef &IR) override final;
+ void cycleStart() override;
+ Status execute(InstRef &IR) override;
void
notifyInstructionIssued(const InstRef &IR,
Modified: llvm/trunk/tools/llvm-mca/FetchStage.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/FetchStage.h?rev=339823&r1=339822&r2=339823&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/FetchStage.h (original)
+++ llvm/trunk/tools/llvm-mca/FetchStage.h Wed Aug 15 15:11:05 2018
@@ -23,21 +23,22 @@
namespace mca {
-class FetchStage : public Stage {
+class FetchStage final : public Stage {
using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
InstMap Instructions;
InstrBuilder &IB;
SourceMgr &SM;
-public:
- FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {}
FetchStage(const FetchStage &Other) = delete;
FetchStage &operator=(const FetchStage &Other) = delete;
- bool hasWorkToComplete() const override final;
- Status execute(InstRef &IR) override final;
- void postExecute() override final;
- void cycleEnd() override final;
+public:
+ FetchStage(InstrBuilder &IB, SourceMgr &SM) : IB(IB), SM(SM) {}
+
+ bool hasWorkToComplete() const override;
+ Status execute(InstRef &IR) override;
+ void postExecute() override;
+ void cycleEnd() override;
};
} // namespace mca
Modified: llvm/trunk/tools/llvm-mca/RetireStage.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/RetireStage.h?rev=339823&r1=339822&r2=339823&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/RetireStage.h (original)
+++ llvm/trunk/tools/llvm-mca/RetireStage.h Wed Aug 15 15:11:05 2018
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
/// \file
///
-/// This file defines the retire stage of an instruction pipeline.
+/// This file defines the retire stage of a default instruction pipeline.
/// The RetireStage represents the process logic that interacts with the
/// simulated RetireControlUnit hardware.
//
@@ -23,22 +23,21 @@
namespace mca {
-class RetireStage : public Stage {
+class RetireStage final : public Stage {
// Owner will go away when we move listeners/eventing to the stages.
RetireControlUnit &RCU;
RegisterFile &PRF;
+ RetireStage(const RetireStage &Other) = delete;
+ RetireStage &operator=(const RetireStage &Other) = delete;
+
public:
RetireStage(RetireControlUnit &R, RegisterFile &F)
: Stage(), RCU(R), PRF(F) {}
- RetireStage(const RetireStage &Other) = delete;
- RetireStage &operator=(const RetireStage &Other) = delete;
- virtual bool hasWorkToComplete() const override final {
- return !RCU.isEmpty();
- }
- virtual void cycleStart() override final;
- virtual Status execute(InstRef &IR) override final { return Stage::Continue; }
+ bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
+ void cycleStart() override;
+ Status execute(InstRef &IR) override { return Stage::Continue; }
void notifyInstructionRetired(const InstRef &IR);
void onInstructionExecuted(unsigned TokenID);
};
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