[PATCH] D50804: DAG: Fix isKnownNeverNaN for basic non-sNaN cases

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 15 13:34:43 PDT 2018


arsenm created this revision.
arsenm added a reviewer: spatel.
Herald added a subscriber: wdng.

fadd/fsub/fmul need to worry about infinities as well as fdiv.

No test because the combines that care about the non-sNaN case are interfered with by matching compare and select patterns in the IR.


https://reviews.llvm.org/D50804

Files:
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp


Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3641,11 +3641,15 @@
   switch (Opcode) {
   case ISD::FADD:
   case ISD::FSUB:
-  case ISD::FMUL: {
+  case ISD::FMUL:
+  case ISD::FDIV:
+  case ISD::FREM:
+  case ISD::FSIN:
+  case ISD::FCOS: {
     if (SNaN)
       return true;
-    return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
-           isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
+    // TODO: Need isKnownNeverInfinity
+    return false;
   }
   case ISD::FCANONICALIZE:
   case ISD::FEXP:
@@ -3668,15 +3672,6 @@
   case ISD::SELECT:
     return isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
            isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
-  case ISD::FDIV:
-  case ISD::FREM:
-  case ISD::FSIN:
-  case ISD::FCOS: {
-    if (SNaN)
-      return true;
-    // TODO: Need isKnownNeverInfinity
-    return false;
-  }
   case ISD::FP_EXTEND:
   case ISD::FP_ROUND: {
     if (SNaN)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D50804.160902.patch
Type: text/x-patch
Size: 1101 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180815/76c207ea/attachment.bin>


More information about the llvm-commits mailing list