[llvm] r339779 - [PowerPC] Enhance the selection(ISD::VSELECT) of vector type
Nemanja Ivanovic via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 15 08:30:36 PDT 2018
Author: nemanjai
Date: Wed Aug 15 08:30:36 2018
New Revision: 339779
URL: http://llvm.org/viewvc/llvm-project?rev=339779&view=rev
Log:
[PowerPC] Enhance the selection(ISD::VSELECT) of vector type
To make ISD::VSELECT available(legal) so long as there are altivec instruction,
otherwise it's default behavior is expanding.
Use xxsel to match vselect if vsx is open, or use vsel.
In order to do not write many patterns in td file, promote (for vector it's
bitcast) all other type into v4i32 and only pattern match vselect of v4i32 into
vsel or xxsel.
Patch by wuzish
Differential revision: https://reviews.llvm.org/D49531
Modified:
llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
llvm/trunk/test/CodeGen/PowerPC/vec_select.ll
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=339779&r1=339778&r2=339779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Aug 15 08:30:36 2018
@@ -4647,14 +4647,6 @@ void PPCDAGToDAGISel::Select(SDNode *N)
CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
return;
}
- case ISD::VSELECT:
- if (PPCSubTarget->hasVSX()) {
- SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
- CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
- return;
- }
- break;
-
case ISD::VECTOR_SHUFFLE:
if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
N->getValueType(0) == MVT::v2i64)) {
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=339779&r1=339778&r2=339779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Aug 15 08:30:36 2018
@@ -586,6 +586,8 @@ PPCTargetLowering::PPCTargetLowering(con
AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
setOperationAction(ISD::SELECT, VT, Promote);
AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
+ setOperationAction(ISD::VSELECT, VT, Promote);
+ AddPromotedToType (ISD::VSELECT, VT, MVT::v4i32);
setOperationAction(ISD::SELECT_CC, VT, Promote);
AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
setOperationAction(ISD::STORE, VT, Promote);
@@ -626,7 +628,6 @@ PPCTargetLowering::PPCTargetLowering(con
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
setOperationAction(ISD::FPOW, VT, Expand);
setOperationAction(ISD::BSWAP, VT, Expand);
- setOperationAction(ISD::VSELECT, VT, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
setOperationAction(ISD::ROTL, VT, Expand);
setOperationAction(ISD::ROTR, VT, Expand);
@@ -649,6 +650,7 @@ PPCTargetLowering::PPCTargetLowering(con
setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
setOperationAction(ISD::SELECT, MVT::v4i32,
Subtarget.useCRBits() ? Legal : Expand);
+ setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
setOperationAction(ISD::STORE , MVT::v4i32, Legal);
setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
@@ -727,12 +729,6 @@ PPCTargetLowering::PPCTargetLowering(con
setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
- setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
- setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
- setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
- setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
- setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
-
// Share the Altivec comparison restrictions.
setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td?rev=339779&r1=339778&r2=339779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrAltivec.td Wed Aug 15 08:30:36 2018
@@ -1051,6 +1051,10 @@ def : Pat<(v4f32 (ftrunc v4f32:$vA)),
def : Pat<(v4f32 (fnearbyint v4f32:$vA)),
(VRFIN $vA)>;
+// Vector selection
+def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
+ (VSEL $vC, $vB, $vA)>;
+
} // end HasAltivec
def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">;
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td?rev=339779&r1=339778&r2=339779&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrVSX.td Wed Aug 15 08:30:36 2018
@@ -870,7 +870,8 @@ let Uses = [RM] in {
"xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
def XXSEL : XX4Form<60, 3,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
- "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
+ "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm,
+ [(set v4i32:$XT, (vselect v4i32:$XC, v4i32:$XB, v4i32:$XA))]>;
def XXSLDWI : XX3Form_2<60, 2,
(outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
Modified: llvm/trunk/test/CodeGen/PowerPC/vec_select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vec_select.ll?rev=339779&r1=339778&r2=339779&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vec_select.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vec_select.ll Wed Aug 15 08:30:36 2018
@@ -1,7 +1,100 @@
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-linux-gnu -mattr=+altivec | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck %s -check-prefix=CHECK-VSX
+; RUN: llc -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s -mtriple=powerpc64le-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=CHECK-NOVSX
-; CHECK: vsel_float
-define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
- %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
- ret <4 x float> %vsel
+define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
+entry:
+ %m = fcmp oeq <4 x float> %c, %d
+ %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
+ ret <4 x float> %v
}
+; CHECK-VSX-LABLE: test1
+; CHECK-VSX: xvcmpeqsp [[REG1:(vs|v)[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test1
+; CHECK-NOVSX: vcmpeqfp v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <2 x double> @test2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) {
+entry:
+ %m = fcmp oeq <2 x double> %c, %d
+ %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b
+ ret <2 x double> %v
+}
+; CHECK-VSX-LABLE: test2
+; CHECK-VSX: xvcmpeqdp [[REG1:(vs|v)[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, [[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test2
+; CHECK-NOVSX: fcmp
+; CHECK-NOVSX: fcmp
+; CHECK-NOVSX: blr
+
+define <16 x i8> @test3(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) {
+entry:
+ %m = icmp eq <16 x i8> %c, %d
+ %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b
+ ret <16 x i8> %v
+}
+; CHECK-VSX-LABLE: test3
+; CHECK-VSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test3
+; CHECK-NOVSX: vcmpequb v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <8 x i16> @test4(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) {
+entry:
+ %m = icmp eq <8 x i16> %c, %d
+ %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b
+ ret <8 x i16> %v
+}
+; CHECK-VSX-LABLE: test4
+; CHECK-VSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test4
+; CHECK-NOVSX: vcmpequh v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
+entry:
+ %m = icmp eq <4 x i32> %c, %d
+ %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %v
+}
+; CHECK-VSX-LABLE: test5
+; CHECK-VSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test5
+; CHECK-NOVSX: vcmpequw v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
+
+define <2 x i64> @test6(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c, <2 x i64> %d) {
+entry:
+ %m = icmp eq <2 x i64> %c, %d
+ %v = select <2 x i1> %m, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %v
+}
+; CHECK-VSX-LABLE: test6
+; CHECK-VSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
+; CHECK-VSX: xxsel v2, v3, v2, v[[REG1]]
+; CHECK-VSX: blr
+
+; CHECK-NOVSX-LABLE: test6
+; CHECK-NOVSX: vcmpequd v[[REG1:[0-9]+]], v4, v5
+; CHECK-NOVSX: vsel v2, v3, v2, v[[REG1]]
+; CHECK-NOVSX: blr
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