[PATCH] D50070: [X86] Improved sched models for X86 CMPXCHG* instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: lib/Target/X86/X86SchedSandyBridge.td:953
+  let Latency = 6;
+  let NumMicroOps = 3;
+  let ResourceCycles = [3, 1, 1];
----------------
My best guess is 6 uops and 8 latency like the other Intel CPUs.

Resource cycles
Port015 - 1 cycle (equivalent to 0156 on other Intel CPUs)
Port05 - 2 cycles (equivalent to the Port06 on other Intel CPUs)
Port4 - 1 cycle
Port23 - 2 cycle


https://reviews.llvm.org/D50070