[llvm] r339407 - [WebAssembly] Gate i64x2 and f64x2 on -wasm-enable-unimplemented
Heejin Ahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 9 16:58:52 PDT 2018
Author: aheejin
Date: Thu Aug 9 16:58:51 2018
New Revision: 339407
URL: http://llvm.org/viewvc/llvm-project?rev=339407&view=rev
Log:
[WebAssembly] Gate i64x2 and f64x2 on -wasm-enable-unimplemented
Summary:
i64x2 and f64x2 operations are not implemented in V8, so we normally
do not want to emit them. However, they are in the SIMD spec proposal,
so we still want to be able to test them in the toolchain. This patch
adds a flag to enable their emission.
Reviewers: aheejin, dschuff
Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits
Differential Revision: https://reviews.llvm.org/D50423
Patch by Thomas Lively (tlively)
Modified:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=339407&r1=339406&r2=339407&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Thu Aug 9 16:58:51 2018
@@ -35,6 +35,12 @@ using namespace llvm;
#define DEBUG_TYPE "wasm-lower"
+// Emit proposed instructions that may not have been implemented in engines
+cl::opt<bool> EnableUnimplementedWasmSIMDInstrs(
+ "wasm-enable-unimplemented-simd",
+ cl::desc("Emit potentially-unimplemented WebAssembly SIMD instructions"),
+ cl::init(false));
+
WebAssemblyTargetLowering::WebAssemblyTargetLowering(
const TargetMachine &TM, const WebAssemblySubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) {
@@ -59,9 +65,11 @@ WebAssemblyTargetLowering::WebAssemblyTa
addRegisterClass(MVT::v16i8, &WebAssembly::V128RegClass);
addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
addRegisterClass(MVT::v4i32, &WebAssembly::V128RegClass);
- addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
addRegisterClass(MVT::v4f32, &WebAssembly::V128RegClass);
- addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
+ if (EnableUnimplementedWasmSIMDInstrs) {
+ addRegisterClass(MVT::v2i64, &WebAssembly::V128RegClass);
+ addRegisterClass(MVT::v2f64, &WebAssembly::V128RegClass);
+ }
}
// Compute derived properties from the register classes.
computeRegisterProperties(Subtarget->getRegisterInfo());
Modified: llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll?rev=339407&r1=339406&r2=339407&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll Thu Aug 9 16:58:51 2018
@@ -1,5 +1,7 @@
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
-; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 | FileCheck %s --check-prefixes CHECK,SIMD128-VM
+; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,SIMD128-VM
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 | FileCheck %s --check-prefixes CHECK,NO-SIMD128
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128 -fast-isel | FileCheck %s --check-prefixes CHECK,NO-SIMD128
@@ -121,6 +123,7 @@ define <4 x i32> @mul_v4i32(<4 x i32> %x
; ==============================================================================
; CHECK-LABEL: add_v2i64
; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: i64x2.add $push0=, $0, $1{{$}}
@@ -132,6 +135,7 @@ define <2 x i64> @add_v2i64(<2 x i64> %x
; CHECK-LABEL: sub_v2i64
; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: i64x2.sub $push0=, $0, $1{{$}}
@@ -143,6 +147,7 @@ define <2 x i64> @sub_v2i64(<2 x i64> %x
; CHECK-LABEL: mul_v2i64
; NO-SIMD128-NOT: i64x2
+; SIMD128-VM-NOT: i64x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: i64x2.mul $push0=, $0, $1{{$}}
@@ -204,6 +209,7 @@ define <4 x float> @mul_v4f32(<4 x float
; ==============================================================================
; CHECK-LABEL: add_v2f64
; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: f64x2.add $push0=, $0, $1{{$}}
@@ -215,6 +221,7 @@ define <2 x double> @add_v2f64(<2 x doub
; CHECK-LABEL: sub_v2f64
; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: f64x2.sub $push0=, $0, $1{{$}}
@@ -226,6 +233,7 @@ define <2 x double> @sub_v2f64(<2 x doub
; CHECK-LABEL: div_v2f64
; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: f64x2.div $push0=, $0, $1{{$}}
@@ -237,6 +245,7 @@ define <2 x double> @div_v2f64(<2 x doub
; CHECK-LABEL: mul_v2f64
; NO-SIMD128-NOT: f64x2
+; SIMD129-VM-NOT: f62x2
; SIMD128: .param v128, v128{{$}}
; SIMD128: .result v128{{$}}
; SIMD128: f64x2.mul $push0=, $0, $1{{$}}
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