[PATCH] D50328: [X86][SSE] Combine (some) target shuffles with multiple uses

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

ping?



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Comment at: test/CodeGen/X86/2012-01-12-extract-sv.ll:12
+; CHECK-NEXT:    vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]
+; CHECK-NEXT:    vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
 ; CHECK-NEXT:    vinsertf128 $1, %xmm0, %ymm0, %ymm0
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RKSimon wrote:
> greened wrote:
> > Can we make this test less brittle by using FileCheck variables?  This goes for pretty much every test in this patch.
> I'm sorry but no - its been repeatedly proven that using update_llc_test_checks.py on the majority of x86 tests is the way forward - it speeds up creation of tests (x86 by far has the highest test coverage), makes regeneration of checks trivial and it prevents dodgy code being 'hidden' (either on purpose or by accident). Additionally many x86 subtargets have different instruction behaviours depending on the registers used so hidng the registers behind regexps make it that more difficult to track.
Just to be clear, this isn't just a regalloc diff - there is a codegen change here - the xmm0 value on line 12 is no longer dependent on the pervious perm that was on line 9.


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Comment at: test/CodeGen/X86/avx512-intrinsics-fast-isel.ll:6498
+; X86-NEXT:    vpmuludq %xmm3, %xmm1, %xmm3
+; X86-NEXT:    vpaddq %xmm2, %xmm3, %xmm2
 ; X86-NEXT:    vpsllq $32, %xmm2, %xmm2
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greened wrote:
> Make this less brittle with FileCheck variables.
Again, there is a codegen change here.


Repository:
  rL LLVM

https://reviews.llvm.org/D50328