[PATCH] D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng created this revision.
kito-cheng added reviewers: asb, apazos, rogfer01.
Herald added subscribers: llvm-commits, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, mgrang, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar.

Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address.


Repository:
  rL LLVM

https://reviews.llvm.org/D50496

Files:
  lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  lib/Target/RISCV/RISCVInstrFormats.td
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoD.td
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/MC/RISCV/rv64i-pseudos.s
  test/MC/RISCV/rvd-pseudos.s
  test/MC/RISCV/rvf-pseudos.s
  test/MC/RISCV/rvi-pseudos.s

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