[PATCH] D50491: [DAGCombiner][AMDGPU][Mips] Fold bitcast with volatile loads if the resulting load is legal for the target.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added a reviewer: efriedma.
Herald added subscribers: jfb, atanasyan, jrtc27, arichardson, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, sdardis.

I'm not sure if this patch is correct or if it needs more qualifying somehow. Bitcast shouldn't change the size of the load so it should be ok? We already do something similar for stores. We'll change the type of a volatile store if the resulting store is Legal or Custom. I'm not sure we should be allowing Custom there...

I was playing around with converting X86 atomic loads/stores(except seq_cst) into regular volatile loads and stores during lowering. This would allow some special RMW isel patterns in X86InstrCompiler.td to be removed. But there's some floating point patterns in there that didn't work because we don't fold (f64 (bitconvert (i64 volatile load))) or (f32 (bitconvert (i32 volatile load))).


Repository:
  rL LLVM

https://reviews.llvm.org/D50491

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AMDGPU/copy-illegal-type.ll
  test/CodeGen/Mips/cconv/return-hard-fp128.ll
  test/CodeGen/Mips/cconv/return-hard-struct-f128.ll
  test/CodeGen/Mips/msa/bitcast.ll

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