[llvm] r339252 - [RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 8 07:45:45 PDT 2018
Author: asb
Date: Wed Aug 8 07:45:44 2018
New Revision: 339252
URL: http://llvm.org/viewvc/llvm-project?rev=339252&view=rev
Log:
[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate
Match the GNU assembler in supporting immediate operands for these
instructions even when the reg-reg mnemonic is used.
Differential Revision: https://reviews.llvm.org/D50046
Patch by Kito Cheng.
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s
llvm/trunk/test/MC/RISCV/rv32i-invalid.s
llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s
llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s
llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=339252&r1=339251&r2=339252&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Wed Aug 8 07:45:44 2018
@@ -550,6 +550,37 @@ def : InstAlias<"csrci $csr, $imm", (CSR
def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>;
def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
+let EmitPriority = 0 in {
+def : InstAlias<"add $rd, $rs1, $imm12",
+ (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"and $rd, $rs1, $imm12",
+ (ANDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"xor $rd, $rs1, $imm12",
+ (XORI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"or $rd, $rs1, $imm12",
+ (ORI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sll $rd, $rs1, $shamt",
+ (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
+def : InstAlias<"srl $rd, $rs1, $shamt",
+ (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
+def : InstAlias<"sra $rd, $rs1, $shamt",
+ (SRAI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
+let Predicates = [IsRV64] in {
+def : InstAlias<"addw $rd, $rs1, $imm12",
+ (ADDIW GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sllw $rd, $rs1, $shamt",
+ (SLLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
+def : InstAlias<"srlw $rd, $rs1, $shamt",
+ (SRLIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
+def : InstAlias<"sraw $rd, $rs1, $shamt",
+ (SRAIW GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
+} // Predicates = [IsRV64]
+def : InstAlias<"slt $rd, $rs1, $imm12",
+ (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sltu $rd, $rs1, $imm12",
+ (SLTIU GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+}
+
//===----------------------------------------------------------------------===//
// Pseudo-instructions and codegen patterns
//
Modified: llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s?rev=339252&r1=339251&r2=339252&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-aliases-invalid.s Wed Aug 8 07:45:44 2018
@@ -11,5 +11,13 @@ li t4, foo # CHECK: :[[@LINE]]:
negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
+sll x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+srl x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+sra x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+
+sll x2, x3, -1 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+srl x2, x3, -2 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+sra x2, x3, -3 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
+
foo:
.space 4
Modified: llvm/trunk/test/MC/RISCV/rv32i-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32i-invalid.s?rev=339252&r1=339251&r2=339252&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32i-invalid.s Wed Aug 8 07:45:44 2018
@@ -69,6 +69,7 @@ csrrci x0, 43, %pcrel_lo(d) # CHECK: :[[
ori a0, a1, %hi(foo) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-2048, 2047]
andi ra, sp, %pcrel_hi(123) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [-2048, 2047]
xori a2, a3, %hi(345) # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [-2048, 2047]
+add a1, a2, (a3) # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-2048, 2047]
## uimm12
csrrw a0, %lo(1), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095]
@@ -126,7 +127,6 @@ sraw t0, s2, zero # CHECK: :[[@LINE]]:1:
# Invalid operand types
xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
-add a1, a2, (a3) # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
# Too many operands
add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s?rev=339252&r1=339251&r2=339252&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv64i-aliases-invalid.s Wed Aug 8 07:45:44 2018
@@ -8,5 +8,21 @@ rdinstreth x29 # CHECK: :[[@LINE]]:1: er
rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
+sll x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+srl x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+sra x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+
+sll x2, x3, -1 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+srl x2, x3, -2 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+sra x2, x3, -3 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
+
+sllw x2, x3, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+srlw x2, x3, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+sraw x2, x3, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+
+sllw x2, x3, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+srlw x2, x3, -2 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+sraw x2, x3, -3 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
+
foo:
.space 8
Modified: llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s?rev=339252&r1=339251&r2=339252&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s Wed Aug 8 07:45:44 2018
@@ -111,3 +111,21 @@ negw x31, x1
# CHECK-INST: addiw t6, ra, 0
# CHECK-ALIAS: sext.w t6, ra
sext.w x31, x1
+
+# The following aliases are accepted as input but the canonical form
+# of the instruction will always be printed.
+# CHECK-INST: addiw a2, a3, 4
+# CHECK-ALIAS: addiw a2, a3, 4
+addw a2,a3,4
+
+# CHECK-INST: slliw a2, a3, 4
+# CHECK-ALIAS: slliw a2, a3, 4
+sllw a2,a3,4
+
+# CHECK-INST: srliw a2, a3, 4
+# CHECK-ALIAS: srliw a2, a3, 4
+srlw a2,a3,4
+
+# CHECK-INST: sraiw a2, a3, 4
+# CHECK-ALIAS: sraiw a2, a3, 4
+sraw a2,a3,4
Modified: llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s?rev=339252&r1=339251&r2=339252&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rvi-aliases-valid.s Wed Aug 8 07:45:44 2018
@@ -155,3 +155,41 @@ sfence.vma
# CHECK-INST: sfence.vma a0, zero
# CHECK-ALIAS: sfence.vma a0
sfence.vma a0
+
+# The following aliases are accepted as input but the canonical form
+# of the instruction will always be printed.
+# CHECK-INST: addi a2, a3, 4
+# CHECK-ALIAS: addi a2, a3, 4
+add a2,a3,4
+
+# CHECK-INST: andi a2, a3, 4
+# CHECK-ALIAS: andi a2, a3, 4
+and a2,a3,4
+
+# CHECK-INST: xori a2, a3, 4
+# CHECK-ALIAS: xori a2, a3, 4
+xor a2,a3,4
+
+# CHECK-INST: ori a2, a3, 4
+# CHECK-ALIAS: ori a2, a3, 4
+or a2,a3,4
+
+# CHECK-INST: slli a2, a3, 4
+# CHECK-ALIAS: slli a2, a3, 4
+sll a2,a3,4
+
+# CHECK-INST: srli a2, a3, 4
+# CHECK-ALIAS: srli a2, a3, 4
+srl a2,a3,4
+
+# CHECK-INST: srai a2, a3, 4
+# CHECK-ALIAS: srai a2, a3, 4
+sra a2,a3,4
+
+# CHECK-INST: slti a2, a3, 4
+# CHECK-ALIAS: slti a2, a3, 4
+slt a2,a3,4
+
+# CHECK-INST: sltiu a2, a3, 4
+# CHECK-ALIAS: sltiu a2, a3, 4
+sltu a2,a3,4
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