[llvm] r339078 - AMDGPU: cvt_pk_rtz_f16 canonicalizes

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Aug  6 16:01:31 2018
New Revision: 339078

URL: http://llvm.org/viewvc/llvm-project?rev=339078&view=rev
Log:
AMDGPU: cvt_pk_rtz_f16 canonicalizes

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
    llvm/trunk/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp?rev=339078&r1=339077&r2=339078&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp Mon Aug  6 16:01:31 2018
@@ -4336,7 +4336,8 @@ bool AMDGPUTargetLowering::isKnownNeverN
     // one?
     return false;
   }
-  case AMDGPUISD::FMUL_LEGACY: {
+  case AMDGPUISD::FMUL_LEGACY:
+  case AMDGPUISD::CVT_PKRTZ_F16_F32: {
     if (SNaN)
       return true;
     return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&

Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=339078&r1=339077&r2=339078&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Mon Aug  6 16:01:31 2018
@@ -6791,6 +6791,7 @@ bool SITargetLowering::isCanonicalized(S
   case AMDGPUISD::DIV_FIXUP:
   case AMDGPUISD::FRACT:
   case AMDGPUISD::LDEXP:
+  case AMDGPUISD::CVT_PKRTZ_F16_F32:
     return true;
 
   // It can/will be lowered or combined as a bit operation.
@@ -6863,6 +6864,18 @@ bool SITargetLowering::isCanonicalized(S
   case ISD::UNDEF:
     // Could be anything.
     return false;
+
+  case ISD::INTRINSIC_WO_CHAIN: {
+    unsigned IntrinsicID
+      = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    // TODO: Handle more intrinsics
+    switch (IntrinsicID) {
+    case Intrinsic::amdgcn_cvt_pkrtz:
+      return true;
+    default:
+      break;
+    }
+  }
   default:
     return denormalsEnabledForType(Op.getValueType()) &&
            DAG.isKnownNeverSNaN(Op);

Modified: llvm/trunk/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll?rev=339078&r1=339077&r2=339078&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fcanonicalize-elimination.ll Mon Aug  6 16:01:31 2018
@@ -827,6 +827,16 @@ define <2 x half> @v_test_canonicalize_i
   ret <2 x half> %canonicalized
 }
 
+; GCN-LABEL: {{^}}v_test_canonicalize_cvt_pkrtz:
+; GCN: s_waitcnt
+; GCN-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1
+; GCN-NEXT: s_setpc_b64
+define <2 x half> @v_test_canonicalize_cvt_pkrtz(float %a, float %b) {
+  %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float %b)
+  %canonicalized = call <2 x half> @llvm.canonicalize.v2f16(<2 x half> %cvt)
+  ret <2 x half> %canonicalized
+}
+
 ; Avoid failing the test on FreeBSD11.0 which will match the GCN-NOT: 1.0
 ; in the .amd_amdgpu_isa "amdgcn-unknown-freebsd11.0--gfx802" directive
 ; CHECK: .amd_amdgpu_isa
@@ -852,6 +862,7 @@ declare half @llvm.cos.f16(half) #0
 declare float @llvm.minnum.f32(float, float) #0
 declare float @llvm.maxnum.f32(float, float) #0
 declare double @llvm.maxnum.f64(double, double) #0
+declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #0
 
 attributes #0 = { nounwind readnone }
 attributes #1 = { "no-nans-fp-math"="true" }